SystemC Verification Working Group (VWG)
The Verification Working Group (VWG) is responsible for defining verification extensions to the SystemC language standard, as well as enriching the SystemC reference implementation by offering add-on libraries to ease the deployment of a verification methodology based on SystemC. These libraries are the UVM-SystemC library and the SystemC Verification library (SCV).
Chair: Stephan Gerth, Fraunhofer Institute For Integrated Circuits
Vice Chair: Bas Arts, NXP Semiconductors
The UVM-SystemC Library 1.0-alpha1 was released in December 2015, and then version 1.0-beta1 was released in December 2017 as a public review release. This release contains the UVM-SystemC Language Reference Manual and the proof-of-concept implementation. The library is compatible with Accellera SystemC 2.3.0 through 2.3.2 and was tested on RH6, RH7, and others. Bug reports and fixes submitted during the public review are now under analysis by the SystemC Verification Working Group.
SystemC Verification Library
The SystemC Verification Library 2.0.1, an update to SCV 2.0, was released in December 2017. This release contains an implementation of the verification extensions for Accellera SystemC 2.3.2 and is compatible with IEEE 1666. Examples and support for recent compilers is also included. The document can be accessed here.
- Compatible with IEEE 1666-2011 through Accellera SystemC 2.3.2
- Wide-spread compilers support (Visual C++, GCC, clang)
- OS support for Windows, RHEL and Ubuntu Linux, OS X
- Numerous bug fixes
SystemC is one of the key languages used for verification activities. Beyond SystemC’s built-in capabilities, verification extensions to its API are needed to avoid reinventing the same mechanism all over again and to provide a stable framework onto which tools suppliers can build added value. As SystemC is a system-level specification methodology, this includes the application of verification approaches on abstract levels, besides hardware potentially also covering RTOS and software.
The current SystemC Verification (SCV) library provides a common set of APIs that are used as a basis to verification activities with SystemC (generation of values under constraints, transaction recording, etc.). These APIs are implemented in all major SystemC simulators available on the market.
As verification needs in SystemC evolve and communication with other languages is more and more frequent, additions to the existing set of APIs are required. For example, these additions will also focus on coverage analysis and temporal assertion checking mechanisms and their interfacing and/or integration into the SystemC language. Standardizing these additions is crucial to allow seamless migration of models from the environment of one tool supplier to another. This integration process also includes the analysis and evaluation of interfaces to existing Accellera verification approaches like UVM and their seamless integration into a SystemC-based verification process.
UVM-SystemC evolved from a donation of the funding project Verdi (www.verdi-fp7.eu). It was taken as a baseline to improve Coverage Driven Verification for SystemC verification. More details can be found here: http://accellera.org/resources/articles/accelleras-uvm-in-systemc-standardization-going-universal-for-esl.
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