Subject: [sv-bc] LRM Milestones dates and Committee Voting
From: Vassilios.Gerousis@infineon.com
Date: Fri Feb 27 2004 - 22:51:58 PST
Dear SV members,
SystemVerilog 3.1A draft 5 will be released in few days. There are
many changes provided by good reviewers that are included. SystemVerilog
chairs have extended the review period to help us examine the new changes
and also to ensure consistency in the full LRM. Here is the plan for the
next few weeks:
1- Please provide review comments to each committee. Only editorial comments
and corrections should be considered. Each committee will then
review and process these comments. Any changes will then be sent to
David Smith to have change notices created and posted on the web
site.
David Smith is The Owner Of The LRM.
a- Any Requested change beyond March 10 will not be included into
LRM Draft6.
b- All changes will be posted on the reflector. Please make sure
that the changes are accurate.
2- The voting process will start on March 10. It will be completed by
March 15. Only qualified corporate members can be counted in this
voting process.
a- The voting will be on Draft 5 plus any changes on the web site.
b- You have essentially 5 days to examine the Draft5 and the changes
before
Voting on March 15.
3- On March 15, we will release two versions of the LRM Draft 6:
a- Clean version (no sidebar or comments) will go to the TCC and
Accellera Board for one month review and voting.
b- Committee version (with sidebar and comments) of Draft 6 will be
released to the committee. Reviews will continue. Still send
errata and comments to committee and David Smith. At this
stage
only editorial comments will be accepted.
4- On March 31, the TCC will provide recommendation to the Accellera Board.
5- On April 15, the Accellera Board will complete the vote and approve 3.1A
as an Accellera Standard.
6- On April 8, all editorial changes will be added to the final LRM of 3.1A.
The final Standard will be released on April 15.
a- We ask again your help to ensure that the changes are correct
before they go into the LRM.
7- Between April 8 through June 1, the SV committees will continue to
collect feedback (Errata and Enhancement). Majority of the SV
committee
will take a month of vacation.
a- Errata will be released on biweekly basis on the reflector.
b- The Errata list will be released separately from the original
Standard. We will have versions attached to it.
c- We encourage everyone to continue the feedback process.
d- We will also release "qualified" models on the SystemVerilog
Working Group Reflector. We encourage everyone to add to
this
collection of qualified models.
e- These models will be the primary mechanism for Accellera to
qualify tools.
I encourage everyone to continue the participation in this process
and help to make SystemVerilog 3.1A a successful standard. I want to thank
many of you who helped in this review process.
Best Regards
Vassilios
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