Section 4.2

LRM-147

Changes:

Unpacked arrays can be made of any singular scalar (non-unpacked-array) type. SystemVerilog enhances fixed-size unpacked arrays in that in addition to all other SystemVerilog types, unpacked arrays may also be made of object handles (see Section 11.4) and events (see Section 13.5).

LRM-75 LRM-138

Changes:

Note: SystemVerilog also accepts a single number instead of (not a range) to specify the size of an unpacked arrays, like C. SystemVerilog should accept this type of declaration as a shorthand notation, that is [size] becomes the same as [size-1:0]. For example:

LRM-89

Changes:

Packed arrays can only be made of the single bit types: (bit, logic, reg, wire, and the other net types), and recursively other packed arrays and packed structures. Unpacked arrays can be made up of any type.

 

 

Section 4.3

LRM-82

Changes:

bit [3:0] [7:0] joe [1:10]; // 10 entries of 4 bytes (packed into 32 bits int)

Section 4.6.1

LRM-1

Changes:

This parameter argument is useful when growing or shrinking an existing array. In this situation, src_array is array_name, so the previous values of the array elements are preserved. For example:

Remove Editor’s Note:

Editor’s Note: “parameter” is a Verilog keyword, and “parameterized” models refer to the usage of Verilog “parameters” (see Sections 11.21, 19.6 and 20). Use of the word “parameterized” in this context is not consistent with the Verilog LRM. Suggest using “arguments” (as in Verilog LRM), “formal arguments” or “formals”.

Section 4.8

LRM-1

Changes:

Passing fixed-size arrays as parameters arguments to subroutines requires that the actual parameter argument and the formal argument in the function declaration be of the compatible type and that all dimensions be of the same size.

Remove Editor’s Note:

Editor’s Note: “parameter” is a Verilog keyword, and “parameterized” models refer to the usage of Verilog “parameters” (see Sections 11.21, 19.6 and 20). Use of the word “parameterized” in this context is not consistent with the Verilog LRM. Suggest using “arguments” (as in Verilog LRM), “formal arguments” or “formals”.

Section 4.10.1

LRM-76

Changes:

$display( "%0d entries\n", map imem.num ); // prints "3 entries"