Process — A process is a thread of
one or more programming statements which can be executed independently of other
programming statements. Each initial procedure, always procedure and continuous
assignment statement in Verilog is a separate
process. These are static processes. That is, each time the process starts
running, there is an end to the process. SystemVerilog
adds specialized always procedures, which are also
static processes, and dynamic processes, introduced
by the process keyword. When dynamic processes are started, they can
run without ending. Processes are presented in Section 9.