Verilog does not have
assignment operators or incrementor increment and decrementor decrement operators. SystemVerilog includes the C assignment operators, such as +=, and the C incrementor increment and decrementor decrement operators, ++ and
--.
SystemVerilog also includes
the C incrementor increment and decrementor decrement assignment operators ++i, --i, i++ and i--.
These do not need parentheses when used in expressions. These increment and
decrement assignment operators behave as blocking assignments.
The ===
and !=== !== check
the 4-state explicitly, therefore, X and Z values will either match or
mismatch, never resulting in X. The =?=
and !?= operators treat X or Z as wild cards that match any
value, thus, they too never result in X.
() [] :: .
= += -= *= /= %= &= ^= |= <<= >>=
<<<= >>>= := :/ <=
Editor’s Note: Both BC62a and BC65 added
this new section. I used BC62a.
Braces are also used for
expressions to initialize assign to unpacked arrays. Unlike in C, the expressions must match element for
element, and the braces must match the array dimensions. The type of each
element is matched against the type of the initializer
expression according to the same rules as for a scalar. This means that the
following examples do not give size warnings, unlike the similar assignments
above:
bit
unpackedbits [1:0] = {1,1}; // no size warning as bit can be set to
1
int
unpackedints [1:0] = {1’b1, 1’b1}; // no size warning as int
can be
// set to 1’b1
The syntax of multiple
concatenations can be used for unpacked array expressions initializers as well. E.g. {3{1}} for{1, 1, 1}.
unpackedbits = {2 {y}} for {y, y}
SystemVerilog
determines the context of the braces by looking at the left hand side of an
assignment. If the left hand side is an unpacked array, the braces represent an
unpacked array literal or expression. Outside the context of an assignment on
the right hand side, an explicit cast must be used with the braces to
distinguish it from a concatenation.
The {member:value} or {data type:default value} syntax can also be used:
ab abkey[1:0] = {{a:1, b:1.0}, {int:2, shortreal:2.0}};
It can sometimes be useful
to set array elements to a value without having to keep track of how many
members there are, or what the names are. This can be done with the default
keyword:
initial
unpackedints = {default:2};
// sets elements to 2
For more arrays of
structures, it is useful to specify one or more matching types, as illustrated
under structure expressions, below.
struct {int a; time b;} abkey[1:0];
abkey = {{a:1, b:2ns}, {int:5, time:$time}};
The rules for unpacked
array matching are as follows:
Editor’s Note: Both BC62a and BC65 added
this new section. I used BC62a.
It can sometimes be useful to
set structure members to a value without having to keep track of how many
members there are, or what the names are. This can be done with the default
keyword:
initial
s1 = {default:2}; // sets x and y to
2
The {member:value} or {data_type: default_value} syntax
can also be used:
ab abkey[1:0]
= {{a:1, b:1.0}, {int:2, shortreal:2.0}};
Note that the default
keyword applies to members in nested
structures or elements in unpacked arrays in structures. In fact, it descends
the nesting to a built-in type or a packed array of them.
Similarly, an individual
member can be set to override the general default and the type default:
initial #10 s1 = {default:’1, s
= ""}; // set all to 1 except s to ""
SystemVerilog
determines the context of the braces by looking at the left hand side of an
assignment. If the left hand side is an unpacked structure, the braces
represent an unpacked structure literal or expression. Outside the context of
an assignment on the right hand side, an explicit cast must be used with the
braces to distinguish it from a concatenation.
The matching rules are as
follows:
Editor’s Note: Both BC62a and BC65 added
this new section. I used BC62a.
Unpacked structure and
array variables, literals, and expressions can all be used as aggregate
expressions. A multi-element slice of an unpacked array is can also be used as an
aggregate expression.
Editor’s Note: Both BC62a and BC65 added
this new section. I used BC62a.
As defined in Verilog, if expression1
is true, the operator returns expression2, if false, it returns expression3.
If expression1 evaluates to an ambiguous value
(x or z), then both expression2 and expression3 shall be
evaluated and their results shall be combined, bit by bit.