Section 16.1

LRM-90

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3) It provides a syntactical context that specifies execution in the Reactive region.

Section 16.2

LRM-237

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A typical program contains type and data declarations, subroutines, connections to the design, and one or more procedural code streams. The connection between design and testbench test-bench uses the same interconnect mechanism as used by SystemVerilog to specify port connections, including interfaces. The syntax for the program block is:

LRM-91

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module test(...)

int shared; // variable shared by programs p1 and p1

LRM-92

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A program block can contain one or more initial blocks. It may not contain always blocks, UDP’s UPD’s, modules, interfaces, or other programs.

Section 16.6

LRM-93

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In addition to the normal simulation control tasks ($stop and $finish), a program can use the $exit control task.