Add the following new paragraph at the end:
The
following table contains the default values for SystemVerilog variables.
Type |
Default Initial value |
4 state integral |
‘X |
2 state integral |
‘0 |
real,shortreal |
0.0 |
Enumeration |
First
value in the enumeration |
String |
“” (empty string) |
event |
New event |
class |
null |
chandle (Opaque handle) |
null |
Table 5-1 Default values
module
byte_swap (inout
wire [31:0] A, inout
wire [31:0] B);
wire [31:0] A,B;
alias
{A[7:0],A[15:8],A[
endmodule
This example strips out the
least and most significant bytes from a four byte bus:
module
byte_rip (inout
wire [31:0] W, inout
wire [7:0] LSB, inout
wire [7:0]
MSB);
wire [31:0] W;
wire [7:0]
MSB,LSB;
alias
W[7:0] = LSB;
alias
W[31:24] = MSB;
endmodule
module
overlap(inout
wire [15:0]
bus16, inout
wire [11:0]
low12, inout
wire [11:0]
high12);
wire [15:0] bus16;
wire [11:0] low12, high12;
alias
bus16[11:0] = low12;
alias
bus16[15:4] = high12;
endmodule
module
overlap(inout
wire [15:0]
bus16, inout
wire [11:0]
low12, inout
wire [11:0]
high12);
wire [15:0] bus16;
wire [11:0] low12,high12;
alias
bus16 = {high12,low12[3:0]};
alias
high12[7:0] = low12[11:4];
endmodule