3) It provides a syntactical context that specifies execution in the
Reactive region.
A typical program contains
type and data declarations, subroutines, connections to the design, and one or
more procedural code streams. The connection between design and testbench test-bench uses the same interconnect
mechanism as used by SystemVerilog to specify port connections, including
interfaces. The syntax for the program block is:
module test(...)
int
shared; // variable shared by programs p1 and p1
A program block can contain
one or more initial blocks. It may not contain always blocks, UDP’s UPD’s, modules,
interfaces, or other programs.
In addition to the normal
simulation control tasks ($stop and $finish), a program can use the $exit
control task.