Section 19.2.1

LRM-200

Changes:

module memMod( input  bit req,

    bit clk,

    bit start,

    logic[1:0] mode,

    logic[7:0] addr,

   inout  wire logic[7:0] data,

   output bit gnt,

    bit rdy );

logic avail;

...

endmodule

 

module cpuMod(

input  bit clk,

 bit gnt,

 bit rdy,

inout  wire logic [7:0] data,

output bit req,

 bit start,

 logic[7:0] addr,

 logic[1:0] mode );

...

endmodule

Section 19.2.2

LRM-200

Changes:

The simplest form of a SystemVerilog interface is a bundled collection of variables or nets. When an interface is used as a port, the variables and nets in it are assumed to be ref and inout ports, respectively. The following interface example shows the basic syntax for defining, instantiating and connecting an interface. Usage of the SystemVerilog interface capability can significantly reduce the amount of code required to model port connections.

Section 19.4

LRM-139

Changes:

module m (i2 i);

...

endmodule

 

module s (i2 i);

...

endmodule

 

module top;

i2 i();

 

m u1(.i(i.master));

s u2(.i(i.slave master));

endmodule

LRM-200

Changes:

Note that if no modport is specified in the module header or in the port connection, then all the wires and variables in the interface are accessible with direction inout or ref, as in the examples above.

Section 19.4.1

LRM-200

Changes:

interface simple_bus (input bit clk); // Define the interface

logic req, gnt;

logic [7:0] addr, data;

logic [1:0] mode;

logic start, rdy;

 

modport slave (input req, addr, mode, start, clk,

   output gnt, rdy,

   ref inout data);

 

modport master(input gnt, rdy, clk,

   output req, addr, mode, start,

   ref inout data);

 

endinterface: simple_bus

Section 19.4.2

LRM-200

Changes:

interface simple_bus (input bit clk); // Define the interface

logic req, gnt;

logic [7:0] addr, data;

logic [1:0] mode;

logic start, rdy;

 

modport slave (input req, addr, mode, start, clk,

   output gnt, rdy,

   ref inout data);

 

modport master(input gnt, rdy, clk,

   output req, addr, mode, start,

   ref inout data);

 

endinterface: simple_bus

Section 19.4.3

LRM-200

Changes:

interface simple_bus (input bit clk); // Define the interface

logic req, gnt;

logic [7:0] addr, data;

logic [1:0] mode;

logic start, rdy;

 

modport slave (input req, addr, mode, start, clk,

   output gnt, rdy,

   ref inout data);

 

modport master(input gnt, rdy, clk,

   output req, addr, mode, start,

   ref inout data);

 

endinterface: simple_bus

LRM-235

Changes:

module memMod(interface interface a); // Uses just the interface

logic avail;

always @(posedge a.clk) // the clk signal from the interface

a.gnt <= a.req & avail; // the gnt and req signal in the interface

endmodule

 

module cpuMod(interface interface b);

...

endmodule

Section 19.5.2

LRM-200

Changes:

modport slave (input req, addr, mode, start, clk,

   output gnt, rdy,

   ref inout data,

   import task slaveRead(),

    task slaveWrite());

// import into module that uses the modport

 

modport master(input gnt, rdy, clk,

   output req, addr, mode, start,

   ref inout data,

   import masterRead,

    masterWrite);

// import into module that uses the modport

LRM-196

Changes:

module memMod(interface a); // Uses just the interface

logic avail;

always @(posedge a.clk) // the clk signal from the interface

ab.gnt <= ab.req & avail; // the gnt and req signals in the interface

always @(a.start)

if (a.mode[0] == 1’b0)

a.slaveRead;

else

a.slaveWrite;

endmodule

LRM-236

Changes:

module cpuMod(interface interface b);

enum {read, write} instr = $rand();

logic [7:0] raddr = $rand();

 

always @(posedge b.clk)

if (instr == read)

b.masterRead(raddr); // call the Interface method

// ...

else

b.masterWrite(raddr);

endmodule

Section 19.5.3

LRM-200

Changes:

modport slave( input req, addr, mode, start, clk,

   output gnt, rdy,

   ref inout data,

   export task Read(),

    task Write());

// export from module that uses the modport

 

modport master(input gnt, rdy, clk,

   output req, addr, mode, start,

   ref inout data,

   import task Read(input logic[7:0] raddr),

    task Write(input logic[7:0] waddr));

// import requires the full task prototype

Section 19.5.4

LRM-200

Changes:

modport slave (input req,addr, mode, start, clk,

   output gnt, rdy,

   ref inout data, slaves,

   export Read, Write, countSlaves);

// export from module that uses the modport

 

modport master ( input gnt, rdy, clk,

     output req, addr, mode, start,

     ref inout data,

     import task Read(input logic[7:0] raddr),

     task Write(input logic[7:0] waddr));

// import requires the full task prototype

Section 19.6

LRM-200

Changes:

modport slave( input req, addr, mode, start, clk,

   output gnt, rdy,

   ref inout data,

   import task slaveRead(),

    task slaveWrite());

// import into module that uses the modport

 

modport master(input gnt, rdy, clk,

   output req, addr, mode, start,

   ref inout data,

   import task masterRead(input logic[AWIDTH-1:0] raddr),

    task masterWrite(input logic[AWIDTH-1:0] waddr));

// import requires the full task prototype