Section 1

LRM-1

Changes:

      Pass by reference subroutine parameters arguments.

Remove Editor’s note:

Editor’s Note: “parameter” is a Verilog keyword, and “parameterized” models refer to the usage of Verilog “parameters” (see Sections 11.21, 19.6 and 20). Use of the word “parameterized” in this context is not consistent with the Verilog LRM. Suggest using “arguments” (as in Verilog LRM), “formal arguments” or “formals”.

LRM-237

Changes:

Verification Functionality: Reusable, reactive testbench test-bench data-types and functions.