Section 8.1

LRM-118

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Verilog provides two overlapping methods for procedurally adding and removing drivers for variables: the force/release force/release statements and the assign/deassign statements. The force/release statements can also be used to add or remove drivers for nets in addition to variables. A force statement targeting a variable that is currently the target of an assign will override that assign; however, once the force is released, the assign’s effect again will be visible.

Section 8.2

LRM-123

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The size of the left-hand side of an assignment forms the context for the right hand side expression. If the left-hand side is smaller than the right hand side, and information may be lost, and a warning can be given.

Section 8.3

LRM-119

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unique if((a==0) || (a==1)) $display("0 or 1");

else if (a == 2) $display("2");

else if (a == 4) $display("4"); // values 3,5,6,7 will cause an error

LRM-120

In Verilog, there are three types of case statements, introduced by case, casez and casex. With SystemVerilog, each of these can be qualified by priority or unique. A priority case shall act on the first match only. A unique case shall guarantee no overlapping case values, allowing the case items to be evaluated in parallel. If the case is qualified as priority or unique, the simulator shall issue an error message if an unexpected case value is found. By specifying unique or priority, it is not necessary to code a default case to trap unexpected case values. For example:

 

Note: by specifying unique or priority, it is not necessary to code a default case to trap unexpected case values. For example:

Section 8.8

LRM-121

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SystemVerilog has break and continue for a clean way to break out of or continue the execution of loops. The Verilog-2001 disable can also be used to break out of or continue a loop, but is more awkward than using break or continue. The disable is also allowed to disable a named block, which does not contain the disable statement. If the block is currently executing, this causes control to jump to the statement immediately after the block. If the block is a loop body, it acts like a continue. If the block is not currently executing, the disable has no effect.

Section 8.9

LRM-1

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If the expression denotes a clocking-domain input or inout (see Section 15), the event control operator uses the synchronous values, that is, the values sampled by the clocking event. The expression may also denote a clocking-domain name (with no edge qualifier) to be triggered by the clocking event.

 

A variable used with the event control can be any one of the integral data types (see Section 3.3.1) or string. The variable may be either a simple variable or a ref argument (variable passed by reference); it may be a member of an array, associative-array, or object (class instance) of the aforementioned types. Objects (handles) and aggregate types are not allowed.

 

Event control variables can include array subscript expressions, in which case the index expression is evaluated only once when the event control statement is executed. Likewise, an object data member in an event control will block until that particular data member changes value, not when the handle to the object is modified. For example:

 

Packer p = new;        // Packet 1

Packet q = new;        // Packet 2

fork

@(p.status);         // Wait for status in Packet 1 to change

p = q;               // Has no effect on the wait in Process 1

join_none

 

// @(p.status) continues to wait for status of Packet 1 to change

Section 8.10

LRM-10

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Passing an argument by reference is a unique parameter argument passing qualifier, different from input, output, or inout. Combining ref with any other qualifier is illegal. For example, the following declaration results in a compiler error:

Remove:

Editor’s Note: This new operator needs to be added to the operator precedence table and other sections describing operator rules (signed/unsigned/2-state/4-state/real operands, etc.).

LRM-87

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Move section 8.10 and insert it in between existing Section 13.5.1 and 13.5.2 making 8.10 content the new 13.5.2 and renumbering existing 13.5.2 and beyond.

Section 8.11

LRM-109

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Remove entire section:

8.11 Assignment expressions within event controls

SystemVerilog allows assignment expressions to be used in an event control, e.g. @((a = b + c)). The event control shall only be sensitive to changes in the result of the expression on the right-hand side of the assignment. It shall not be sensitive to changes on the left-hand side expression.

LRM-122

Remove editor’s note:

 

Editor’s Note: I took the liberty to elevate the previous paragraph its own section, as it introduces a syntax not in the Verilog language.