Join Us for Accellera Day at DVCon U.S. 2017

DVCon US 2017Monday, February 27

Design & Verification Conference and Exhibition
DoubleTree Hotel, San Jose, CA

Accellera invites you to join us as we open DVCon U.S. with a day filled with insights into technologies that you can apply immediately and those that will help to define the future.



12:00pm-1:30pmAccellera Sponsored Luncheon


5:00pm -7:00pmDVCon Expo and Booth Crawl

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DVCon U.S. 2017 Mobile App

Review the program and save sessions to your personalized conference schedule using the free DVCon U.S. 2017 mobile app, available for download today.

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Tutorial 1: Creating Portable Stimulus Models with the Upcoming Accellera Standard

Portability of reusable test cases has long been a goal for semiconductor verification and validation teams. No one wants to "reinvent the wheel" by having to rewrite similar tests again and again. While the widely accepted Accellera Universal Verification Methodology (UVM) standard enabled reuse of testbench components and constrained-random tests at the IP and block level, the limitations in terms of reuse at subsystem and full-chip level as well as lack of portability across execution platforms required a fresh look at addressing the portable stimulus and test challenge. Accellera Systems Initiative formed the Portable Stimulus Working Group (PSWG) in early 2015 to do just that. The group's charter is to define a portable test and stimulus standard specification to permit the creation of a single representation/model, usable by a variety of users across different levels of integration under different configurations, enabling the generation of different implementations that run on a variety of execution platforms, including, but not limited to, simulation, emulation, FPGA prototyping, and post-silicon. With such a specification in place, EDA vendors can produce tools that automatically generate stimulus, results checks, and coverage metrics tuned for a particular target.

The first version of the Accellera Portable Test and Stimulus Standard (PSS) is nearing completion. This timely tutorial presents an introduction to the standard’s main features leveraging a series of usage examples defined by PSWG members that represent many of the common challenges faced in today’s multi-core designs. The tutorial will show with actual coding examples how the verification and portability challenges of these examples are met using the standard.

Attendees will learn how to:

  • Understand and develop abstract, portable test and stimulus models for their chip designs
  • Use PSS constraints to guide randomization of both data and control flow to describe a legal scenario space to be verified
  • Target use of existing low-level sequences or drivers in the generation of tests
  • Execute generated tests across platforms from simulation, emulation, FPGA prototype, and post-silicon to verify a complete chip or multi-chip system
  • Specify and gather coverage metrics at every step to assess verification completeness

David Brownell - Analog Devices, Inc.
Sharon Rosenberg - Cadence Design Systems, Inc.
Tom Fitzpatrick - Mentor Graphics Corp.
Adnan Hamid - Breker Verification Systems, Inc.
Srivatsa Vasudevan - Synopsys, Inc.
Karthick Gururaj - Vayavya Labs Pvt., Ltd.
Faris Khundakjie - Intel Corp.

Barbara Benjamin - Accellera Systems Initiative

Accellera Luncheon

Accellera Day 2017 at DVCon will be filled with exciting technical insights you'll be able to apply immediately to your projects. In the middle of the day we'll take a break and gather for lunch where we will have a presentation by Accellera that will include the 2017 Technical Excellence award, a look forward to the worldwide DVCon events, latest news, and working group activities. After that, we will have a town hall meeting covering topics including:

  • Follow up questions from the Portable Stimulus morning tutorial
  • Future directions for the UVM Working Group
  • SystemC working groups activity including what’s new

All attendees of the Monday tutorials are invited to this Accellera-sponsored luncheon.

Mark Glasser - NVIDIA Corporation
Trevor Weiman - Intel Corp.
David Brownell - Analog Devices, Inc.

Adam Sherer - Accellera Systems Initiative

Tutorial 2: Introducing IEEE 1800.2 – The Next Step for UVM

UVMBy all measures, UVM is the most successful verification standard ever created in the EDA community. And that's no boast. From inception to today, it has swept through project teams worldwide which makes it ready for the next step with the IEEE. The IEEE 1800 committee is completing the work on UVM as the 1800.2 standard. This rigorous review of the Accellera work has resulted in some changes that improve UVM as a standard for interoperability. The tutorial will focus on those changes and how you can prepare for the IEEE standard today. As we review those changes, we will also examine the impact it will have on your existing verification environments including how to debug and regold those environments improving your ability to share verification IP among globalized teams.

Tom Alsop - Intel Corp.
Srivatsa Vasudevan - Synopsys, Inc.
Mark Glasser - NVIDIA Corporation
Srinivasan Venkataramanan - CVC Pvt., Ltd.
Krishna Thottempudi - Qualcomm, Inc.

Adam Sherer - Accellera Systems Initiative

Tutorial 3: SystemC Design and Verification – Solidifying the Abstraction Above RTL

SystemCEach year the EDA community makes critical advances in SystemC. As we do, the momentum toward SystemC as the primary point of entry above RTL becomes more tantalizing. Will this be the year your team makes the leap? This tutorial could answer that question for you.

We will focus on three key components that could help you make that decision: design, modeling, and testbench. We'll start by examining the latest advances in the SystemC language including the synthesizable subset and CCI configuration. A discussion of modeling for high-performance simulation will follow to complete our view of the overall design. Of course, we need to verify this fast-running design with a testbench approach that can be reused at RTL so we'll discuss how to apply the emerging UVM-SystemC standard. We'll complete the tutorial with a Q/A session with all of our presenters focusing on the remaining work they see to help you make the leap to the SystemC abstraction.

Trevor Wieman - Intel Corp.
Peter Frey - Mentor Graphics Corp.

Adam Sherer - Accellera Systems Initiative

DVCon Expo Booth Crawl

Booth CrawlDVCon is doing it again! You won't want to miss the annual DVCon Booth Crawl on the exhibit floor featuring cocktails and conversations in a casual environment with the DVCon exhibitors. Mingle from booth to booth while enjoying food and drinks provided by exhibitors.

Win big at the booth crawl!By attending the Booth Crawl you'll be automatically entered into a drawing for a $500 VISA gift card. The winner must be present to win and will be announced Monday night.

Booth Crawl Participants



Thank you to our 2017 Global Sponsors

CadenceMentor GraphicsSynopsys