UVM-AMS Proposed Working Group


The Accellera board of directors recently approved the formation of a Proposed Working Group (PWG) to collect industry interest and requirements for mixed-signal verification and standardization. The PWG will focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard.

Chair: Patrick Lynch, Xilinx
Secretary: Joen Westendorp, NXP Semiconductors

Kick-off Meeting

Wednesday, May 22
10:00am – 4:00pm CEST
NXP Semiconductors, Schatzbogen 7, 81829
Munich, Germany

(Meeting registration is now closed)

The initial meeting will cover presentations on industry best practices, discuss scope and requirements, and explore directions for standardization. Participants in the PWG do not need to be from Accellera member companies. Companies that have already shown an interest in standardization in this area include Xilinx, NXP Semiconductors, Infineon Technologies, Maxim Integrated, ams AG, ST Microelectronics, Dialog Semiconductor, Cirrus Logic, and Renesas.


There have been many discussions in recent years about the need to make UVM more mixed-signal aware. The purpose of the PWG is to explore the need further, and to determine the level of industry interest and commitment in moving forward with standardization efforts to create a UVM-AMS standard. The UVM-AMS PWG will assess the benefits of creating analog and mixed-signal extensions to UVM and determine if a path to standardization is feasible.

Various proposals have been presented at recent DVCon events addressing the need for AMS extensions for UVM to enrich and improve the verification of analog/mixed-signal products and applications. Most of these proposals offer similar capabilities but often use a different implementation to resolve existing constraints enforced by UVM or by limitations caused by mixing languages such as SystemVerilog and Verilog-AMS. The objective of the PWG is to explore the need for standardized UVM mixed-signal extensions, and offer a unified approach for mixed-signal verification.

Join this Proposed Working Group

Accellera Proposed Working Groups are open to participation by both Accellera members and the community* (non-members). If you are an employee of a member company and would like to join this working group, click here (requires login) and click Join Group. If your company is not an Accellera member company, please contact This email address is being protected from spambots. You need JavaScript enabled to view it. to sign up for the PWG.

* For non-member participants some conditions apply. See the Accellera Policies & Procedures, Section 13 "Proposed Working Group Formation" for details.