Subject: Face to Face Meeting Plans for September 18 for the entire SV com mittee
From: Vassilios.Gerousis@Infineon.Com
Date: Fri Aug 23 2002 - 07:14:15 PDT
Hello everyone,
We are putting plans to have our first face to face meetings as an SV committee. I have established an sv@eda.org reflector, but I have not activated it yet.
We will do a full day meeting to discuss the following:
a- Milestones and synchronization effort.
b- Status and progress of each committee.
-- Issues and enhancement list.
-- Topics to be addressed at the full committee.
c- Generation and reviewing SV LRM.
d- New donation presentations.
e- Other topics as I get more feedback from you.
I will announce the place. The duration is a full day. I am working with the chairs to develop a detailed agenda. Although we may have a teleconference call, I strongly suggest that you attend in person.
Another reminder especially for new comers in the committees, we have selected September 15 as the deadline for any donations to be considered for SystemVerilog 3.1. The second reminder is to reiterate that the donation must be complementary to what has been donated as well as what exist today in SystemVerilog 3.0. It is the responsibility of the donors to examine their donations and ensure this important criteria. I will send the new donations to the committees as they arrive.
Best Regards
Vassilios
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Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
Telephone: +49-89-234-21342 BalanSt. 73
Fax: +49-89-234-23650 D-81541 Munich
email: Vassilios.Gerousis@infineon.com Germany
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