Subject: Progress towards SystemVerilog 3.1
From: Vassilios.Gerousis@Infineon.Com
Date: Tue Sep 03 2002 - 22:36:41 PDT
SV committee members,
At the start of SystemVerilog 3.1 the SV chairs has set a process
together and
also has set three major milestones. We have also set a deadline for
accepting additional
complimentary donations.
In the last two months the chairs and co-chairs of SystemVerilog have made
tremendous progress towards getting our first milestone done. We have
assembled over
60 to 70 members with varying expertise in many fields of verification,
design and formal
methods. We have great and proven technologies given to us to standardize
from the
best in the industry. We have enough donations. This by itself is a large
task. Every
Chair and Co-Chair of SystemVerilog has accepted the challenge to work,
modify and
create a portion of the standard that will ultimately become ONE
SystemVerilog LRM 3.1.
We have established four committees to focus in several areas and
attract the
appropriate expertise. This allow better focus on each topic area. This also
gives us better
opportunities for debate in a smaller group rather in a large committee.
Each committee
has established a set of goals which are created by each committee to
fulfill the task we
have started. In my simple words, the following committee have taken the
challenge to
provide:
1- SystemVerilog Basic Committee: This intended to allow a forum for EDA
vendors who
are implementing SystemVerilog 3.0 to help change SystemVerilog 3.1 for
better implementation.
The committee should give priority to real implementation rather than just
opinion.
2- SystemVerilog Enhancement: The committee will address all additions to
the language. Today
they are focusing on SystemVerilog Testbench. However, other SV committees
will have to
give this committee assignment like C-interface language construct,
modification of SystemVerilog to
allow better embedding of OVL, etc.
3- SystemVerilog C interface: This committee will address SystemVerilog API,
establish a c-interface
and provide good standard for applications like coverage.
4- SystemVerilog Assertion: The committee will consider the wealth of
Accellera in terms properties,
and assertions, and people expertise to create a powerful assertion-based
methodology. Embedding
of assertion using Verilog methodology is one the primary focus. The second
focus to make sure we
are aligned with PSL (Property Specification Language from the Formal
Committee).
Based on advise by several people and also by the chairs, we will
create a SystemVerilog
committee that all those committee will report to. Each committee is
responsible for their portion
of the LRM. All technical debate and acceptance will be done in each
committee.
SV committee will assemble and review. This has been in the planning process
for two
months, and I am in discussion with potential chair for this committee.
As we move from milestone one to milestone two, we will have more
frequent meetings for SV
committee. We have established an email reflector sv@eda.org (not
activated). In the last two months before milestone three happen, we will
have a weekly meeting of the SV committee, until we produce a final draft
that we can take to the Accellera Board. Please be prepared for hard work.
Our first SystemVerilog meeting is now planned for September 17. We
will present more detail.
Please put on your calendars the week of November 11/12 for our second face
to face meeting. In February,
please expect a weekly meeting of this committee.
This is an exciting time, and this is a big challenge that many of
us has accepted. It is time for
fighting parties (you know who you are) to start working as a team. Our main
focus is to deliver SystemVerilog
3.1 by DAC 2003. The SystemVerilog 3.0 was efficiently done. Although we
have a larger task, I have no doubt that this team although much larger,
will make it happen.
So I urge each one of you to focus on our activities. Stop the EDA rivalry
and consider for once the user community. SystemVerilog 3.1 will deliver
smarter verification and smarter design (synthesis). This is our
team logo.
Please, if you ideas of improvement, please send those directly to
me or an of the SystemVerilog
chair.
Let us fulfill our first milestone soon. And do not forget SystemVerilog
Delivers smarter verification and smarter
synthesis.
Best Regards
Vassilios
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Dr. Vassilios Gerousis
Chief Scientist
Infineon Technologies
DAT CS, MchB
D-81541 Munich
Germany
BalanSt. 73
Telephone: +49-89-234-21342
Fax: +49-89-234-23650
email: Vassilios.Gerousis@infineon.com
Site Map:
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
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