Subject: Arrangement For SV Committee Meeting On September 17.
From: Vassilios.Gerousis@Infineon.Com
Date: Tue Sep 10 2002 - 23:48:31 PDT
Hello Everyone,
I want to thank Synopsys for helping to organize the facility for
this large number of people. This has not been an easy job. My thanks go to
Amanda for working hard with all kinds of constraints that we imposed on
her.
I will send an updated agenda with a process plan for generating a
final SV 3.1 LRM.
ARRANGEMENT
==================
1- The Place: Please use Mapquest to get directions.
The meeting will take place in the Glacier conference room in bldg. C on the
first floor and the address is 700 East Middelfield Road, Mountain View,
California 94043.
2- Date and Time: September 17. We will start promptly at 9:30 and end
around 4:30 PM.
3- Audio Conference:
Toll Free Dial In Number: (877)288-4427
Int'l Access/Caller Paid Dial In Number: (734)414-0267
PARTICIPANT CODE: 880406
Please RSVP to the phone conference call: Send me name as well as
times planned for the conference.
Due to the large number of attendees, and conference room structure:
a- You WILL not be able to hear every discussion. Please do
not ask for repetition.
b- Do not ask for slides/materials in advance.
4- Final List of Attendees
1- Ambar Sarkar
ambar.sarkar@paradigm-works.com
2- KC Chen [kchen@verplex.com]
3- Erich Marschner, Cadence Design Systems
4- David W. Smith - Synopsys -- Chairman of
SystemVerilog
5- Dennis Brophy, Model Technology / Mentor
Graphics - Accellera Chairman
6- Richard C. Ho (rho@0-in.com)
7- Kevin Cameron [dkc@grfx.com] National
Semiconductor
8- Bassam Tabbara [bassam@novas.com]
9- Simon Davidmann [simond@co-design.com]
10- Yatin Trivedi - Consultant -- Chairman
of C Interface Committee.
11- Karen Pieper [Karen.Pieper@synopsys.com]
12- David Fong [dfong@s3graphics.com]
13- Grant Martin - [gmartin@cadence.com]
14- Faisal Haque - Cisco, fhaque@cisco.com
- Chairman of SystemVerilog Assertion Committee.
15- Siamak Arya [siamak@telairity.com]
Telairity Semiconductor, Inc.
16- Jayant Nagda - Synopsys.
17- Stephen Meier - Synopsys.
18- Vassilios Gerousis - Infineon
Technologies. - Chairman of SystemVerilog Committeen and TCC chairman.
19- Rajeev K. Ranjan
[rajeev@realintent.com]
20- Kurt Takara [ktakara@0-In.com]
21- Alec Stanculescu [alec@fintronic.com]
22- Stuart Sutherland.
23- David Kelf Dave Kelf
[davek@co-design.com]
24- Stefenen Boyd Stefen Boyd
[stefen@boyd.com]
25- Mehdi Mohtashemi mehdi@synopsys.com
26- Prakash Narain [prakash@realintent.com]
27- Darrell Parham [Darrell.Parham@eng.sun.com]
28- Michael McNamara (Verisity)
29- Harry Foster (Verplex).
30- Tom Fitzpatrick [fitz@co-design.com]
31- Prakash Narain [prakash@realintent.com]
32- Ghassan Khoory [Ghassan.Khoory@synopsys.com]
33- Brad.Pierce@synopsys.com
34- Tarak Parikh [tarak@athdl.com]
35- Joseph Lu [Juin-Yeu.Lu@Sun.COM]
More to follow Tomorow.
Best Regards
Vassilios
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Dr. Vassilios Gerousis
Chief Scientist
Infineon Technologies
DAT CS, MchB
D-81541 Munich
Germany
BalanSt. 73
Telephone: +49-89-234-21342
Fax: +49-89-234-23650
email: Vassilios.Gerousis@infineon.com
Site Map:
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
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