Subject: Typedefs and generate
From: Gordon Vreugdenhil (gvreugde@synopsys.com)
Date: Tue Sep 17 2002 - 07:47:10 PDT
Typedefs can expose elaboration dependency problems similar to
those that occur with an "upwards defparam" in the presence
of Verilog2001 generate statements.
Consider the following:
typedef T;
defparam some_param = T'(10000);
generate
if (some_condition)
typedef int T;
else
typedef byte T;
endgenerate
This is essentially an obscure upwards defparam since the
defparam relies on a type whose definition is created
conditionally. One can create similar issues with the use
of type parameters to modules that exist outside the scope
of the generate.
My basic suggestion is that type definitions should follow
the same fundamental restriction as defparams in the
presence of generate. The basic statement would be something
like:
"A typedef inside a generate may not define the actual
type of a forward definition that exists outside the
scope of the forward definition."
This is a slightly more restrictive wording than the defparam
wording but other choices end up causing difficult problems
in terms of sequencing the elaboration (top-down elaboration
is not possible through the generate block).
Gord
-- ---------------------------------------------------------------------- Gord Vreugdenhil gvreugde@synopsys.com Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054 Synopsys Inc., Beaverton OR
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