Subject: Re: Typedefs and generate
From: Gordon Vreugdenhil (gvreugde@synopsys.com)
Date: Tue Sep 17 2002 - 08:39:28 PDT
Karen Pieper wrote:
>
> Gord, in just reading your sentence, I'm not sure I understand what it
> means. Does this need
> an example of what the scope of the forward definition means?
First, in re-reading this myself, what I meant to say was
"immediate scope". Perhaps "block" would be even better.
The idea here is to allow something like:
generate
typedef T;
<other stuff including uses of T>
typedef int T;
endgenerate
or
generate
if (condition) begin
typedef T;
<other stuff including uses of T>
typedef int T;
end
endgenerate
since the actual definition and forward definition occur in
the same actual (pre-elaboration) scope/block.
What would be disallowed would be:
generate
typedef T;
<other stuff including uses of T>
begin
typedef int T;
end
endgenerate
or equivalent cases where the actual type definition doesn't
occur in the same block (immediate scope) as the forward
definition.
This would also disallow the case that I originally presented.
Gord.
> K
>
> At 07:47 AM 9/17/02 -0700, Gordon Vreugdenhil wrote:
> >Typedefs can expose elaboration dependency problems similar to
> >those that occur with an "upwards defparam" in the presence
> >of Verilog2001 generate statements.
> >
> >Consider the following:
> >
> > typedef T;
> >
> > defparam some_param = T'(10000);
> >
> > generate
> > if (some_condition)
> > typedef int T;
> > else
> > typedef byte T;
> > endgenerate
> >
> >
> >This is essentially an obscure upwards defparam since the
> >defparam relies on a type whose definition is created
> >conditionally. One can create similar issues with the use
> >of type parameters to modules that exist outside the scope
> >of the generate.
> >
> >My basic suggestion is that type definitions should follow
> >the same fundamental restriction as defparams in the
> >presence of generate. The basic statement would be something
> >like:
> > "A typedef inside a generate may not define the actual
> > type of a forward definition that exists outside the
> > scope of the forward definition."
> >
> >This is a slightly more restrictive wording than the defparam
> >wording but other choices end up causing difficult problems
> >in terms of sequencing the elaboration (top-down elaboration
> >is not possible through the generate block).
> >
> >Gord
> >--
> >----------------------------------------------------------------------
> >Gord Vreugdenhil gvreugde@synopsys.com
> >Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054
> >Synopsys Inc., Beaverton OR
-- ---------------------------------------------------------------------- Gord Vreugdenhil gvreugde@synopsys.com Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054 Synopsys Inc., Beaverton OR
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