Subject: Re: always_comb semantics
From: Michael McNamara (mac@verisity.com)
Date: Fri Oct 04 2002 - 13:21:17 PDT
Gordon Vreugdenhil writes:
>
> It is certainly uncomputable whether a variable is always set.
> That is one of the reasons I didn't bring up that aspect
> (Superlog, btw, does require that). SystemVerilog, correctly,
> doesn't require checks for this.
>
> Gord.
Now how is this?
One simply creates a surrounding synthetic context which sets the
variable, and then evaluates the reaching definition for each node in
the graph, and if the synthetic definition is never in the set of
reaching definitions of any use, then you have proven the variable is
always set before being used.
You will end up with a conservative definition : you will be correct
for every variable that you state will be set before being used;
however some variables that you say _could_ be used before being set,
will in truth never suffer this fate, because proving that every
possible path through a flow graph could be taken is an uncomputable
problem.
[See pp 610 of Compilers, Princples & Techniques]
-mac
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