Subject: Re: $sv-ec Minutes / Pointers
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Oct 14 2002 - 15:49:30 PDT
....
> 3. Extensions list discussion
> A. Separated Reference and Pointer. Only address Reference in 3.1.
> B. References:
> Kevin has the responsibility to handle the passing of arrays and other
> objects that are passed by reference to the C API as part of the SV-CC
> committee.
>
> Kevin is pushing to have an agreed upon definition of memory layout.
> David indicated that this is the responsibility of the SV-CC to define.
>
> Since the var solution is sufficient for the known requirements for
> pass by reference we will delay any further discussion until after all
> of the objects that can be passed is defined. This was suggested by
> Kevin.
My question at the moment is:
Is everyone that is currently implementing a SystemVerilog simulator intending
to implement structs and arrays that are directly representable in C (i.e.
unpacked 2-state data) with the same memory layout as C?
My understanding is that that is what SuperLog does, but it isn't explicit in
the 3.0 standard that SV works that way.
Kev.
This archive was generated by hypermail 2b28 : Mon Oct 14 2002 - 15:51:08 PDT