Subject: RE: Second SystemVerilog Face to Face meeting - December 4 - Mentor Graphics - San Jose
From: David W. Smith (david.smith@synopsys.com)
Date: Fri Nov 08 2002 - 08:25:33 PST
I will be there.
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
http://www.synopsys.com
-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Vassilios.Gerousis@Infineon.Com
Sent: Thursday, November 07, 2002 9:57 PM
To: sv-ac@eda.org; sv-bc@eda.org; sv-ec@eda.org; sv-cc@eda.org
Subject: Second SystemVerilog Face to Face meeting - December 4 - Mentor
Graphics - San Jose
Importance: High
Hello SystemVerilog Members,
We will hold our second SystemVerilog meeting in San Jose. Our
host will be Dennis Brophy at Mentor Grphics. This is a face to face
meeting and your presence is encouraged. We will try to provide a
teleconference, but the phone is not idea for large crowd in a big
conference.
Date: December 4th.
Time: 9 AM Until 3:00 AM.
Place: Mentor Graphics in San Jose.
Planned Agenda:
1- SV committee status (all four committees).
2- Scheduling of event and semantics for SV 3.1 (Possibly Peter
Flake): A presentation of how Testbench, Assertion, SV 3.0 are connected
together in terms of events, synchronization and associated semantics.
3- Technical Presentation:
a- Assertion (SVA): Latest SVA LRM.
b- Direct-C (SVC): Latest SVC LRM
c- Changes expected or proposed by basic: Proposals
d- Enhancement beyond Testbench (SVT): Latest LRM and
completed proposals.
4- Patent Discussions: I will present my understanding of 0-in
patent and ask opinions on how to proceed. I am also in discussion with
0-in in the hope that they cooperate with Accellera.
5- SV analysis.
6- SV Chairs meeting (3:00 to 5:00 PM) -- For the chairs only.
You are required to RSVP in order to hold a place for you.
Seating is limited.
Best Regards
Vassilios
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