Subject: Fwd: BOUNCE sv-bc@eda.org: Non-member submission from [Peter Flake
>Date: Thu, 21 Nov 2002 03:24:08 -0800 (PST)
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: Thu Nov 21 2002 - 09:47:55 PST
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Thu Nov 21 2002 - 09:47:19 PST
>From: owner-sv-bc@eda.org
>To: owner-sv-bc@eda.org
>Subject: BOUNCE sv-bc@eda.org: Non-member submission from [Peter Flake
><Peter.Flake@synopsys.com>]
>
> >From owner-sv-bc Thu Nov 21 03:24:02 2002
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>Date: Wed, 20 Nov 2002 14:57:11 +0000
>To: <Brad.Pierce@synopsys.com>
>From: Peter Flake <Peter.Flake@synopsys.com>
>Subject: Re: Attribute names
>Cc: <sv-bc@server.eda.org>
>In-Reply-To: <HPECIHFPOFICGBKPKCGMEEOJCCAA.bpierce@synopsys.com>
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>Hi Brad,
>
>I do not think that attributes have a namespace. There is no restriction
>on multiple declarations within a module.
>
>Peter.
>
>At 07:02 PM 11/18/02 -0800, Brad Pierce wrote:
>>Which space do attribute names live in?
>>
>>In V2K, they have their own namespace. In SystemVerilog, however,
>>according to section 12.9, there is only one namespace, not 7 namespaces
>>as in V2K. But that section makes no specific mention of attributes.
>>
>>Also, why is there no way to declare attributes and their
>>types? Wouldn't a design project be employing some limited set of
>>project-standard attributes, not inventing new attributes all over the
>>place as they go along. If so, it might make more sense to declare these
>>standard attributes in $root. Likewise, a tool could provide a header
>>file that declares (and documents) the set of attributes it understands.
>>
>>It might also be useful to enable declarations that restrict the kind of
>>objects to which a particular attribute can be attached. Maybe one
>>attribute only makes sense for interfaces and another only for
>>functions. It would be convenient if this could be declared as part of
>>their type.
>>
>>-- Brad
>>
>>
>>
>>