Subject: Re: ( i++ += ++i++ )
From: Steven Sharp (sharp@cadence.com)
Date: Thu Nov 21 2002 - 15:51:14 PST
>
>Expression level assigments are not a productivity boost.
>
I agree with Adam on this. Just because C has certain unusual features
doesn't mean we need to shove them all into Verilog.
I don't have a big issue with assignment operators (e.g. i &= 1;). They
are occasionally used in C, though a lot of their uses (like setting and
clearing bits in variables by ORing and ANDing with masks) can already
be done more conveniently in other ways in Verilog (such as by assigning
values to specific bits with bit and part selects). I don't think they
are worth adding, but they don't cause serious problems.
Treating assignments as expressions is another matter. This is one of
those quirks of C that causes at least as many problems as it solves.
It causes much worse problems in Verilog. It introduces a new source
of side effects into expression evaluation, which causes problems for
things like continuous assignments. Having variables changing values
during expression evaluation means that continuous assignments don't
behave like combinational logic. This is undesirable. I am strongly
opposed to allowing assignments to be treated as expressions.
I consider the increment and decrement operators to be special cases
of this. I think that "i++" should be treated as an assignment statement,
not an expression. This still allows the most commonly desired usage,
"for (i = 0; i < width; i++)". It avoids the problems of side effects in
expressions, or worrying about order of evaluation or pre-increment versus
post-increment. Usages of increments in array indexes was a cute way
of taking advantage of the auto-increment addressing modes on the PDP-11
in early C compilers. It is hardly a recommended programming style these
days.
Steven Sharp
sharp@cadence.com
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