Subject: Clarification of SV-BC8-2b
From: Dave Rich (David.Rich@synopsys.com)
Date: Sat Nov 23 2002 - 08:57:47 PST
>From the SystemVerilog 3.0 Document
Section 3.7, bottom of page 11.
OLD:
A packed union contains members that are packed structures or arrays of
the same size. This ensures that you can read
back a union member that was written as another member. If any member is
4-state, the whole union is 4-state. A
packed union can also be used as a whole with arithmetic and logical
operators, and its behavior is determined by the
signed or unsigned keyword, the latter being the default.
NEW:
A packed union contains members that are packed structures or arrays of
the same size. This ensures that you can read back a union member that
was written as another member. A packed union can also be used as a
whole with arithmetic and logical operators, and its behavior is
determined by the signed or unsigned keyword, the latter being the
default. If a packed union contains a 2-state member and a 4-state
member, the entire union is 4 state. There is an implicit conversion
from 4-state to 2-state when reading and from 2-state to 4-state when
writing the 2-state bit member.
-- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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