Subject: Clarification for SV-BC18h and 18i
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Nov 25 2002 - 23:03:29 PST
3.1 (Informative) - 2nd para
OLD:
See section 3.3.1.
New
See sections 3.3.1 and 5.6.
5.1 (Informative)
OLD:
Verilog 2001 constants are literals, parameters, localparams and
specparams. Verilog 2001 also has variables and nets. Variables must be
written by procedural statements, and nets must be written by continuous
assignments or ports.
NEW:
Verilog 2001 constants are literals, parameters, localparams and
specparams. Verilog 2001 also has variables and nets. Variables must be
written by procedural statements, and nets must be driven by continuous
assignments or ports. SystemVerilog extends the functionality of
variables by allowing them to either be written by procedural statements
or driven by a continuous assignment. For legacy behavior, a reg
variable retains its Verilog-2001 functionality, whereas a logic
variable is its SystemVerilog replacement.
5.6 Nets, regs, and Other Variables
Replace with:
In Verilog 2001, a net can only be written by one or more continuous
assignments, primitive outputs or through module ports. The resultant
value of multiple drivers is determined by the resolution function of
the net type. If a net on one side of a port is driven by a variable on
the other side, a continuous assignment is implied. The value can be
overridden by a force statement. When released, it returns to resolved
value.
Verilog 2001 also states that reg variables can only be written by one
or more procedural statements, including procedural continuous
assignments. The last write determines the value. The force statement
overrides the procedural assign statement which in turn overrides the
normal assignments. A reg variable cannot be written through a port, it
must go through an implicit continuous assignment
In SystemVerilog, all variables except reg can be written either by one
continuous assignment or primitive output, or by one or more procedural
statements, including procedural continuous assignments. Thus a reg
variable retains its Verilog-2001 usage restrictions, whereas a logic
variable uses the SystemVerilog rules. A variable with one continuous
assignment shall be further classified as a continuous variable,
otherwise it shall be classified as a procedural variable. Note:
SystemVerilog variables may be aggregates of other variables or
elements. These classifications can be applied individually to each
element making up the aggregate using the longest static prefix rules.
See section(TBD-granularity).
A variable can be written through a port. When a port has the same
variable type on both sides, a write to one side writes to the other
side. If a port has a reg type on one side and logic on the other, an
implicit continuous assignment is created because reg and logic are not
the same type.
It shall be an error to have multiple continuous assignments or a
mixture of procedural and continuous assignments writing to the same
variable, even through ports. For the purposes of the preceding rule, a
declared variable initialization or a procedural continuous assignment
is considered a procedural assignment. A force statement is neither a
continuous or procedural assignment.
A force statement on a continuous variable follows the Verilog rules for
nets; a release re-establishes the current value of the driving
statement. A force statement on a procedural variable follows the
Verilog rules for variable
Note the difference between a net declaration with assignment and a
variable initialization:
wire w = vara & varb; // continuous assignment
reg r = consta & constb; // initial assignment
logic v = consta & constb; // initial assignment, can have other
procedural assignments
logic l; // no initial assignment
assign l = vara & varb; // continuous assignment to a logic real circ;
assign circ = 2.0 * PI * R; // continuous assignment to a real
Examples of legal drivers:
assign myvar = myfunc(X); // assumes the return type of myfunc is
compatible with myvar
buf (strong0, strong1) (mybits,w);
Examples of illegal drivers:
assign (strong1,highz0) mybit = ^myotherbits; // If RHS is 1'bx, LHS
needs to drive StH,
bufif0(b2,control,in); // If control is 1'bx, b2 would need to be StH or
StL. All bufif and notif primitives are illegal
pmos(b3,control,in); // All MOS are illegal since they need to pass
strength.
-- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
This archive was generated by hypermail 2b28 : Mon Nov 25 2002 - 23:08:11 PST