Subject: Re: Clarification for SV-BC18h and 18i
From: Dave Rich (David.Rich@synopsys.com)
Date: Tue Nov 26 2002 - 09:58:10 PST
Shalom,
Please suggest the proper wording for me. I have been using and teaching
Verilog for 15 years and have never had a problem with this
interpretation, so it is difficult for me to see where the confusion
lies. Let me dig into this a little further since I still have other
clarifications to write up.
If I have a reg on one side and a net on the other, "something" has to
watch the reg, and when it changes, drive the value onto the net, where
it gets resolved with the other drivers. To me, this is the same as a
continuous assignment. A stronger example is when there are an input
expressions.
module top;
reg [7:0] A;
wire [7:0] W;
logic L;
assign W=A+1;
initial begin A=1; #2 A=0; #3 L=1; end
always @(L) $display(L);
bot b1(A+2,W,L);
bot b2(A,W+3,L);
endmodule
module bot(input wire [7:0] x,y, inout logic z);
always @x $display(x);
always @y $display(y);
initial z = 0;
endmodule
Since modules only introduce scope, what would this SV code look like
after elaboration(or flattened)?
module top; // elaborated pseudo-code
reg A;
wire W;
logic L
assign W=!A;
initial begin A=1; #2 A=0; #3 L=1; end
always @(L) $display(L);
// from b1
wire [7:0] b1.x;
// wire [7:0] b1.y is collapsed with W
// logic b1.z is shared with L
assign b1.x = A+2;
always @b1.x $display(b1.x);
always @W $display(W);
initial L = 0;
// from b2
wire [7:0] b2.x;
wire [7:0] b2.y;
// logic b2.z is shared with L
assign b2.x = A;
assign b2.y = W+3;
always @b2.x $display(b2.x);
always @b2.y $display(b2.y);
initial L = 0;
endmodule
Shalom.Bresticker@motorola.com wrote:
>Your meaning is still not clear to me.
>
>Do you mean simply to emphasize the statement that a reg may not be written
>through a port, only a net ?
>
>If so, then say so explicitly and don't talk about implicit continuous
>assignments, which confuse the issue.
>
>In fact, you should omit talking about implied continuous assignments in the
>previous paragraph as well, which talks about nets.
>
>There is an errata filed on that issue in the 1364-2001 ETF,
>because that description is not quite accurate.
>In fact, it is problematic and misleading.
>
>Shalom
>
>
>
>
>>It means it has to get converted to a net.
>>
>>
>>
>>>The last half-sentence is not clear.
>>>What does "it must go through an implicit continuous assignment" refer to,
>>>and what does it mean?
>>>
>>>
>
>
>
>
>
>
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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