Subject: Re: Clarification for SV-BC18h and 18i
From: Dave Rich (David.Rich@synopsys.com)
Date: Wed Nov 27 2002 - 09:17:55 PST
Shalom,
ETF #54 deals with a different issue, when both sides of a port are
wires. There, I believe, the issue is with defining port collapsing in
the LRM and not allowing an implicit continuous assignments. There still
must be an implicit continuous assignment when the types don't match.
Take your Verilog example and modify the port to an expression. How does
the input rr become St0?
module qq ;
wire rr ;
assign (weak1, weak0) rr = 1'b1 ;
pp pp (!rr ) ;
endmodule
module pp ( rr ) ;
input rr ;
initial #10 $display ("%v", rr ) ;
endmodule
We have explicitly defined the port collapsing behavior for
SystemVerilog variables and left the original behavior of Verilog wires
and reg alone. So I think the work that you are doing defining port
collapsing of wires will fit right into SystemVerilog.
Dave
-- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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