Subject: Re: $sv-ec Logic Data Types need fixing
From: Stefen Boyd (stefen@boyd.com)
Date: Fri Nov 29 2002 - 09:45:09 PST
At 04:50 PM 11/26/2002 -0800, Clifford E. Cummings wrote:
>Attached is an analysis of, and a proposal to fix the SystemVerilog 3.0
>"logic" data type. I'm not sure which committee should take this up. It is
>both a fix and an enhancement.
Cliff,
Looks like you are now trying to revive my "universal"
type proposal that died in committee:
At 04:11 PM 1/18/2002 -0800, Stefen Boyd wrote:
>I would like to propose the following for the
>logic type to make it truly universal:
> 1) If the logic variable is driven by more
> than one source, it will be resolved as
> a wire (strength resolution). This
> includes continuous assignments and
> primitives.
> 2) It's an error to attempt to drive a value
> onto a logic variable AND perform a
> procedural assignment.
> (I'm assuming that module port connections
> that are all logic types will use the same
> shared variable behavior as currently used
> for the logic type. Module port connections
> to a reg or wire will be treated as continuous
> assignments and thus require wire styled
> multiple driver resolution).
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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