Subject: RE: $sv-ec SV 3.1 draft 1 LRM available
From: David W. Smith (david.smith@synopsys.com)
Date: Tue Dec 03 2002 - 14:27:46 PST
Just a clarification so that I can hopefully curtail some of the
responses.
This version contains the testbench donation only. It has not been
through the SV-EC review yet so it is a starting point for SV-EC to work
through many of the details. The donation has been accepted but the
contents of this version of the LRM are still being worked out.
Please feel free to take a copy and look through it. Clearly there are
items that affect each committee so it is valuable for all to see. If
you have issues with the additions please send them to the SV-EC
reflector so we can add them to our issue list and work through them (we
have made much progress already but, still more to come...).
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
http://www.synopsys.com
-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Stuart Sutherland
Sent: Tuesday, December 03, 2002 1:56 PM
To: sv-ac@eda.org; sv-bc@eda.org; sv-ec@eda.org; sv-cc@eda.org
Subject: $sv-ec SV 3.1 draft 1 LRM available
All,
Draft 1 of the SystemVerilog 3.1 is available for you to download and
print. This draft reflects the addition of the TestBench donation, as
specified by the SV-EC committee.
You can download the PDF document from:
http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf
All text that was added in this draft are highlighted as blue text, with
change bars in the margins. There is a lot--it roughly doubles the size
of
the 3.0 LRM!
Stu
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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