Subject: enumeration types in testbench donation and SV 3.0
From: Francoise Martinolle (fm@cadence.com)
Date: Fri Dec 06 2002 - 14:01:39 PST
I was reading the testbench donation on enumeration types and
I am wondering if it is compatible with systemVerilog enumeration types.
In the testbench donation there is an example illustrating the
uses of enumeration typed objects.
enum Colors = {reb, blue, green)
Colors c;
initial
c = green;
c = 1; //illegal in the testbench donation
if (c == 1) // legal in testbench donation
c++; => this goes out of range , not sure if it is legal in the testbench donation
endif
I am wondering if the assignments and comparison and increment operations are legal in system Verilog.
I cannot find anything in the SV lrm to indicate legal operations on enumeration typed objects
except for the sentence in section 3.6 (SV 3.0) which says" the type is checked in assignments, arguments and relational operators (which check the value)."
Francoise
'
This archive was generated by hypermail 2b28 : Fri Dec 06 2002 - 14:02:58 PST