Subject: Logic vs Reg
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Mon Dec 09 2002 - 11:45:17 PST
In VHDL a "driver" is the object that interfaces a process to a net, every VHDL process
that writes to a net has its own driver. A side effect of that is that you can't use a seperate
process to initialze the driver, all processes have to be activated at time zero.
Verilog uses the "reg" declaration to declare a driver that is shared between the processes
in a module. That behavior is useful for behavioral modeling of a block with a single output
driver (mapping to (say) a single set of totempoled transistors), where the jobs of initialization,
reset and regular operation can be handled by seperate processes.
Since there is only one resolved type in Verilog (logic), "reg" has become synonymous with
that type in peoples' minds. However you could expand "reg" to apply to other types, e.g.
real:
reg real foo;
- to create a driver/net pair of type real. If you assume that the resolution function for "real"
is to produce "NaN" when mutiple drivers are active and have different values that would
maybe be useful functionality. It could also be used with structs/unions to create a resolved
version (vs. the shared variable version):
struct foo {...}
module (output rslvd_foo);
reg foo rslvd_foo;
...
- that would create seperately resolved nets for fields in rslvd_foo.
Note: at some point it will be necessary to differentiate between a type that applies to
a single physical wire and one that refers to a group of wires as well as whether it is
resolved or not e.g.:
struct cmplx {real rl,img;}
module rf_mod (inout rf_net);
reg wire cmplx rf_net;
...
- could declare a single wire resolved net of type cmplx with a locally shared driver (the
resolution function would be defined by the user).
Regards,
Kev.
-- National Semiconductor, Tel: (408) 721 3251 2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090
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