Subject: RE: [sv-ec] RE: SystemVerilog Strategy, Plans and Proposal to address issues
From: Bernard Deadman (bdeadman@sdvinc.com)
Date: Tue Dec 17 2002 - 09:13:41 PST
Hi Sandeep,
This thread started in SystemVerilog, but affects VFV - have you looked at
the assertion facilities in SystemVerilog recently?
Try:
http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf
Co-ordination? What co-ordination? The industry doesn't need two
incompatible languages for the same purpose!
Regards
Bernard
At 12:17 PM 12/17/2002 -0500, Sandeep K. Shukla wrote:
>Bernard,
>
>I am confused; could you please clarify if you are answering to Jay in
>the context of a separate thread of discussions that was not on any vfv
>thread, or did I miss something?
>
>Regards
>
>Sandeep
>
>
>______________________________________________
>Dr. Sandeep K. Shukla
>Assistant Professor
>Electrical and Computer Engineering
>Virginia Tech
>Blacksburg, VA 24061
>email:shukla@vt.edu
>URL:http://filebox.vt.edu/users/shukla
>______________________________________________
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