A.6.8, do...while() needs trailing semicolon (;)

Subject: A.6.8, do...while() needs trailing semicolon (;)
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Thu Jan 02 2003 - 16:15:14 PST

• Next message: Srouji, Johny: "Agenda for our next SV-BC tele-call on Monday, January 6th"
• Previous message: Brad Pierce: "ANSI C sequence points and the single-update restriction (Was: More issues)"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

I've confirmed with Co-Design that a do-while loop in SystemVerilog,
as it does in C, requires a trailing semicolon (;).

For example, the following fragment should give a syntax error --

    always begin
    automatic integer i = 10;
    do $display("%d", i); while ((i = i-1)) // need a ; here
    end

I think this means that in A.6.8 (and Syntax 8-4), the do-while
BNF productions should be --

    | do function_statement while ( expression ) ;
                                              ^^^

    | do statement while ( expression ) ;
                                     ^^^

-- Brad

• Next message: Srouji, Johny: "Agenda for our next SV-BC tele-call on Monday, January 6th"
• Previous message: Brad Pierce: "ANSI C sequence points and the single-update restriction (Was: More issues)"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

This archive was generated by hypermail 2b28 : Thu Jan 02 2003 - 16:15:51 PST