Subject: Re: shortreal <-> bit conversion proposal
From: Gordon Vreugdenhil (gvreugde@synopsys.com)
Date: Tue Jan 07 2003 - 08:09:06 PST
Jay Lawrence wrote:
>
> Gord,
>
> This looks fine if we want a separate task for this purpose.
>
> Was the alternative considered that $realtobits() could just be modified
> to accept either a 32 or 64-bit real value and return the corresponding
> width vector? There is some precendent to have $tasks with variable type
> args (i.e. $display). I think the proposal on $cast is proposing to do
> the same thing.
>
> It may be handy if I'm modeling with a real and then determine a
> shortreal provides acceptable precision to not have to change the $tasks
> I use.
Generally this makes sense. A couple of things:
1) return values are not variable in Verilog system functions; this would
be the first overloading that returns different values
2) since real literals are "real", any $realtobits on a literal would
always provide a 64 bit real
On a technical level it is easy to do the overloading but this is a different
kind of overloading than Verilog has permitted before, so I'd like wider
discussion before adopting it.
Gord.
> Just a thought,
>
> Jay
>
> > -----Original Message-----
> > From: Gordon Vreugdenhil [mailto:gvreugde@synopsys.com]
> > Sent: Monday, January 06, 2003 5:09 PM
> > To: SV_BC List
> > Subject: shortreal <-> bit conversion proposal
> >
> >
> > Proposal:
> >
> > ADD:
> >
> > Section 16.7 "shortreal conversions"
> >
> > Verilog 2001 defines a "real" type and functions $realtobits and
> > $bitstoreal to permit exact bit pattern transfers between a
> > real and a
> > 64 bit vector. SystemVerilog adds the "shortreal" type and in a
> > parallel manner, $shortrealtobits and $bitstoshortreal are
> > defined to
> > permit exact bit transfers between a shortreal and a 32 bit vector.
> >
> > [31:0] $shortrealtobits(shortreal_val) ;
> > shortreal $bitstoshortreal(bit_val) ;
> >
> > $shortrealtobits converts from a shortreal number to the 32-bit
> > representation (vector) of that shortreal number. $bitstoshortreal
> > is the reverse of $shortrealtobits; it converts from the
> > bit pattern to
> > a shortreal number.
> >
> >
> >
> > Note: It would probably be better to have the above section become
> > 16.3 and shift 16.3-16.6 down to 16.4-16.7. If so, change
> > "16.7" in the following proposal to "16.3".
> >
> > : The above text is a simply a slightly modified version of
> > the IEEE 2001 text for $bitstoreal and $realtobits.
> >
> >
> >
> > Proposal (dependent on the above being accepted):
> >
> > In Section 3.8:
> >
> > REPLACE:
> >
> > When a shortreal is converted to an int, its value is rounded as
> > in Verilog. So the conversion can lose information. When a
> > shortreal is
> > converted to 32 bits, its bit pattern is preserved, which
> > means it can be
> > converted back to the same value without any loss of
> > information. This
> > technique can also be used for structures, where the $bits
> > attribute gives
> > the size of a structure in bits (the $bits system function is
> > discussed in
> > section 16.2):
> >
> > WITH:
> >
> > When a shortreal is converted to an int or to 32 bits, its value is
> > rounded as in Verilog. So the conversion can lose
> > information. To convert
> > a shortreal to its underlying bit representation without a loss of
> > information,
> > use $shortrealtobits as defined in Section 16.7. To convert from the
> > bit representation of a shortreal value into a shortreal, use
> > $bitstoshortreal as defined in Section 16.7.
> >
> > Structures can be converted to bits preserving the bit
> > pattern, which means
> > they can be converted back to the same value without any loss of
> > information. The following example demonstrates this
> > conversion. In the
> > example, the $bits attribute gives the size of a structure in
> > bits (the
> > $bits system function is discussed in section 16.2):
> >
> >
> > --
> > ----------------------------------------------------------------------
> > Gord Vreugdenhil gvreugde@synopsys.com
> > Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054
> > Synopsys Inc., Beaverton OR
> >
-- ---------------------------------------------------------------------- Gord Vreugdenhil gvreugde@synopsys.com Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054 Synopsys Inc., Beaverton OR
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