Subject: [sv-bc] Fwd: FW: Inconsistent use of error/warnings on priority/unique keyword s
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Mon Jan 20 2003 - 13:45:20 PST
This issue has been forwarded to the sv-bc from Adam Krolnik.
K
>I wanted to note the inconsistency in SV 3.0 with regard to unique and
>priority case/if statements. The current SV 3.1 document still has these
>inconsistencies. Would you consider making the result more consistent as
>proposed below?
>
>
>
>System Verilog 3.0 and draft 1 of SV 3.1 both state:
>
>Section 8.3 (if statement) says, "If either keyword [unique or priority]
>is used, it
>shall be a run-time warning for no condition to match unless there is an
>explicit else."
>
>Next paragraph says, [unique if] ... "A software tool shall issue an
>error if it
>determines that there is a potential overlap in the conditions."
>
>Two paragraphs later, "If the case is qualified as a priority or unique,
>the simulator
>shall issue a warning message if an unexpected case value is found."
>
>
>These statements produce an inconsistent set of requirements when
>unexpected input
>patterns occur.
>
>problem statement unique priority
>no match if warn warn
>overlap if error ----
>no match case warn warn
>overlap case *1 ----
>
>*1. It states "unique case shall guarantee no overlapping cases" but
>provides no
> required result (warning or error) if this guarantee if violated.)
>
>IMHO, if you using these additional keywords to imply behavior, then the
>results
>should be that an error be reported when the behavior is violated. To
>have some
>cases be a warning and some cases be an error provides for the potential
>to overlook
>the serious problem the simulator is referring to. Warnings in general
>are ignored
>and are not considered fatal.
>
>
> Thanks for considering this as a issue to address.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
This archive was generated by hypermail 2b28 : Mon Jan 20 2003 - 13:45:49 PST