Re: [Fwd: [sv-bc] Removal of the SystemVerilog logic data type]


Subject: Re: [Fwd: [sv-bc] Removal of the SystemVerilog logic data type]
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Fri Jan 24 2003 - 15:23:54 PST


At 08:34 AM 1/24/2003, Don Mills wrote:
>- logic is not and never was a universal data type (somebody needs to tell
>Stu to change his presentation)
>- as a matter of fact, logic was removed from SystemVerilog altogether
>yesterday (Stu needs to change his presentation)

Cliff,

I wholly support using the reg data type to do everything a logic data type
can do, and removing the logic data type, ***IF*** it can be done and
maintain full backward compatibility with Verilog-2001. I support the
change because it removes "logic" from the reserved keyword list. But, if
changing reg has any backward compatibility issues at all, then I prefer
keeping the logic data type.

Just to set the record straight, the "presentation" you are referring to, I
assume, is the one I have presented for Accellera and for the Oregon IEEE
chapter. This presentation is based on SystemVerilog 3.0. The logic type
IS in 3.0, and it would be inappropriate to remove it from a presentation
on 3.0. Indeed, if it were removed, nearly every example in the 3.0 LRM
would be invalid. When 3.1 is ratified, I will be updating my presentation
to reflect all the 3.1 data types.

Perhaps calling logic a "universal" data type is too general, but keep in
mind that SV 3.0 makes logic the default type for most circumstances. That
makes it pretty close to universal, if not completely universal. In fact,
in the few places that SV 3.0 says the default data type is something other
than logic, I have noticed the SystemSim Superlog simulator still defaults
to logic, further proving the potential of logic being a universal data
type. The last-write-wins behavior for wired outputs may not be the best
representation of hardware, but syntactically, logic can truly be used
almost universally.

Stu

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Stuart Sutherland Sutherland HDL Inc.
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