Re: [sv-bc] Proposal for SV-BC 19-12

Subject: Re: [sv-bc] Proposal for SV-BC 19-12
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Wed Jan 29 2003 - 09:28:17 PST

Please disregard the postscript of my previous message, since
the underscored names at the end are in conflict with the LRM.
They should be more like --

    wire [7:0] loop[2].x [3:0] [1:0];
    wire [11:0] loop[3].x [5:0] [2:0];
    ...

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Brad
Pierce
Sent: Wednesday, January 29, 2003 8:40 AM
To: sv-bc@eda.org
Subject: [sv-bc] Proposal for SV-BC 19-12

---------------- Proposal ---------------------------------------------

Change 2nd production of type_declaration in A.2.1.3 from --

    | 'typedef'
             interface_identifier
                   { [ constant_expression ] }
                                '.' type_identifier

to

    | 'typedef'
             interface_instance_identifier
                   [ '[' constant_expression ']' ]
                                '.' type_identifier

-------

Add to A.9.3 --

  interface_instance_identifier
           ::=
               identifier

---------------------------------------------------------------------------- 

--

p.s.

Here's an example using generated instances.  I'm not clear on how to do
this sort of thing with arrayed interface instances --

  interface it #(parameter N = 8) (input bit clk) ;
    typedef bit[4*N-1:0] u_t[2*N-1:0][N-1:0] ;
  endinterface

  module m #(parameter N=15) (input bit clk);
    generate
      for ( genvar i = 2 ; i < N ; i++ )
        begin : loop
          it #(i) it_inst() ;
          typedef it_inst.u_t u_t;
          u_t x ;
        end
    endgenerate
  endmodule

should yield something like --

module m (clk);
  input clk;
  wire clk;
  parameter N = 15;
  wire [7:0] loop_2_x [3:0] [1:0];
  wire [11:0] loop_3_x [5:0] [2:0];
  wire [15:0] loop_4_x [7:0] [3:0];
  wire [19:0] loop_5_x [9:0] [4:0];
  wire [23:0] loop_6_x [11:0] [5:0];
  wire [27:0] loop_7_x [13:0] [6:0];
  wire [31:0] loop_8_x [15:0] [7:0];
  wire [35:0] loop_9_x [17:0] [8:0];
  wire [39:0] loop_10_x [19:0] [9:0];
  wire [43:0] loop_11_x [21:0] [10:0];
  wire [47:0] loop_12_x [23:0] [11:0];
  wire [51:0] loop_13_x [25:0] [12:0];
  wire [55:0] loop_14_x [27:0] [13:0];
endmodule

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