[sv-bc] Action Items from 22 January 2003 meeting

Subject: [sv-bc] Action Items from 22 January 2003 meeting
From: Peter Flake (Peter.Flake@synopsys.com)
Date: Mon Feb 03 2003 - 08:46:50 PST

Hi All,

Here are the changes for my action items.  They contain the wording agreed in the slides at the meeting.

The section numbers refer to the SystemVerilog 3.0 document.

Peter.
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In 2.5 add the following at the end

The time literal is interpreted as a realtime value scaled to the current time unit and rounded to the current time precision. Note that if a time literal is used as an actual parameter to a module or interface instance, the current time unit and precision are those of the module or interface instance. 

In 3.2 move time from non_integer type to integer_atom_type
In 3.3 add time as 4-state Verilog-2001 data type, 64 bit integer
In 3.3.1 include time with logic, reg and integer

Remove section 3.4.1
---------------------------------------------------------------------
In section 5.3 replace OLD

"A local parameter is a constant which is calculated at elaboration time, and can depend upon parameters or other local parameters at the top level or in the same module or interface"

with NEW

"A parameter or local parameter can only be set to an expression of literals, parameters or local parameters, genvars, or a constant function of these.  Hierarchical names are not allowed."

Replace OLD

"A specify parameter is also calculated at elaboration time, but it may be modified by the PLI, and so cannot be used to set parameters or local parameters"

with NEW

"A specparam can also be set to an expression containing one or more specparams"

Replace OLD

"A constant declared with the const keyword is calculated after elaboration.  This means that it can contain an expression with any hierarchical path name.  This constant is like a variable which cannot be written"

with NEW

"A constant declared with the const keyword, can only be set to an expression of literals, parameters, local parameters, genvars, a constant function of these, or other constants.  The parameters, local parameters or constant functions can have hierarchical names. This is because the static constants are calculated after elaboration."

-----------------------------------------------------------------------------
In section 13.5, ADD AFTER SECOND PARAGRAPH

If a module is connected to a modport containing an exported task or function, and the module does not define that task or function, then an elaboration error occurs.  Similarly if the modport contains an exported task or function prototype, and the task or function defined in the module does not exactly match that prototype, then an elaboration error occurs.

-------------------------------------------------------------------
Section 13.5.4
REPLACE OLD
"Normally, only one module responds to the task call, e.g. the one containing the appropriate address. Only then should the task write to the result variables. Note multiple export of functions is not allowed, because they must always write to the result"

WITH NEW
"The call to extern forkjoin task countslaves( ); in the example below behaves as
        fork
        top.mem1.a.countslaves;
        top.mem2.a.countslaves;
        join

For a read task, only one module should actively respond to the task call, e.g. the one containing the appropriate address. The tasks in the other modules should return with no effect. Only then should the active task write to the result variables.

Note multiple export of functions is not allowed, because they must always write to the result.

The effect of a disable on an extern forkjoin task is as follows:

If the task is referenced via the interface instance, all task calls should be disabled.
If the task is referenced via the module instance, only the task call to that module instance should be disabled.

If an interface contains an extern forkjoin task, and no module connected to that interface defines the task, then any call to that task reports a run-time error and returns immediately with no effect.

REPLACE OLD EXAMPLE WITH

interface simple_bus (input bit clk); // Define the interface
   logic req, gnt;
   logic [7:0] addr, data;
   logic [1:0] mode;
   logic start, rdy;
   int slaves = 0;
  
   // tasks executed concurrently as a fork/join block
   extern forkjoin task countSlaves();
   extern forkjoin task Read(input logic [7:0] raddr);
   extern forkjoin task Write (input logic [7:0] waddr);
   
   modport slave( input req,addr, mode, start, clk,
                  output gnt, rdy,
                  inout data, slaves,
                  export Read, Write, countSlaves);
        // export from module that uses the modport
        
   modport master(input gnt, rdy, clk,
                  output req, addr, mode, start,
                  inout data,
                  import task Read(input logic[7:0] raddr),
                         task Write(input logic[7:0] waddr));
        // import requires the full task prototype
        
   initial begin
      slaves = 0;
      countSlaves;
      $display ("number of slaves = %d", slaves);
   end

endinterface: simple_bus

module memMod #(parameter int minaddr=0, maxaddr=0;) (interface a);
   logic avail = 1;
   logic [7:0] mem[255:0];

   task a.countSlaves();
      a.slaves++;
   endtask
   
   task a.Read(input logic[7:0] raddr); // Read method
      if (raddr >= minaddr && raddr <= maxaddr) begin
         avail = 0;
         #10 a.data = mem[raddr];
         avail = 1;
      end
   endtask
  
   task a.Write(input logic[7:0] waddr); // Write method
      if (waddr >= minaddr && waddr <= maxaddr) begin
         avail = 0;
         #10 mem[waddr] = a.data;
         avail = 1;
      end
   endtask

endmodule

module cpuMod(interface b);
   typedef enum {read, write} instr;
   instr inst;
   logic [7:0] raddr;
   integer seed;
  
   always @(posedge b.clk) begin
      inst = instr'($dist_uniform(seed, 0, 1));
      raddr = $dist_uniform(seed, 0, 3);
      if (inst == read) begin
        $display("%t begin read %h @ %h", $time, b.data, raddr);
         callr:b.Read(raddr);
        $display("%t end read %h @ %h", $time, b.data, raddr);
      end
      else begin
        $display("%t begin write %h @ %h", $time, b.data, raddr);
         b.data = raddr;
        callw:b.Write(raddr);
        $display("%t end write %h @ %h", $time, b.data, raddr);
      end
   end
  
endmodule

module top;
   logic clk = 0;

   function void interrupt();
      disable mem1.a.Read; // task via module instance
      disable sb_intf.Write; // task via interface instance
      if (mem1.avail == 0) $display ("mem1 was interrupted");
      if (mem2.avail == 0) $display ("mem2 was interrupted");
   endfunction
  
   always #5 clk++;
  
   initial begin
      #28 interrupt();
      #10 interrupt();
      #100 $finish;
   end
  
   simple_bus sb_intf(clk);
  
   memMod #(0,  127)  mem1(sb_intf.slave);
   memMod #(128, 255) mem2(sb_intf.slave);
   cpuMod cpu(sb_intf.master);

endmodule

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