Subject: [sv-bc] SV-EC Proposal: Procedural Assignments to Declared or Implicit Wires - Cliff Cummings to champion the proposal
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Feb 03 2003 - 11:21:27 PST
Hi, All -
"Universal Data Type" apparently has a misconstrued meaning. I would like
to amend the proposal name to something like Procedural Assignments to
Declared or Implicit Wires.
· Verilog-2001 now allows a user to require all declarations by
setting `default_nettype none
· SystemVerilog 3.0 (modified) now allows a user to declare a type
that allows procedural or driver assignments to the same type "logic" but
that does not permit resolved driver assignments (I still think this type
should be called "ulogic")
· We are missing the ability to omit all declarations except for
internal sized-vectors of a generic type. This is what I am trying to solve
with this proposal.
I think we are putting too much emphasis on keeping the user from making a
multi-driver mistake. This has never been a complicated problem to solve in
any of my designs; however, we have added "logic" to address this
corner-case error. I can support this.
There are two bigger problems that we have not addressed:
(1) Making multiple RTL procedural assignments to the same variable in
the same module. For simulation, you can get race-prone last assignment
wins behavior by making procedural assignments to the same variable from
two clocked always blocks, but synthesis tools like Synopsys will warn and
then infer two flip-flops with the outputs anded together, which does not
remotely behave the same as the pre-synthesis simulation. There have been
no proposals to address the multi-procedural-block assignment problem,
which I consider to be a much bigger problem than the multi-driver problem.
I just give the guideline: do make RTL procedural assignments to the same
variable from more than one procedural block.
(2) An RTL coder changes a procedural assignment to a continuous
assignment within a module and forgets to change the declaration or vice
versa. This is not a hard problem to fix, it is just such an annoying and
common mistake and requiring changes to the declaration has no real value
to the design. This is what I am trying to change with the following proposal.
My proposal is to allow wires, declared or implicit, to allow EITHER
procedural assignments OR continuous assignments within a module and that
the behavior of the identifier is consistent with either wires or regs,
depending on how they are used in the module. Advantages:
(1) I don't add any new keywords
(2) I don't have to change the declaration when I change from
procedural to continuous assignments or vice versa - wire can now be used
as a generic, sized variable
(3) Wire is already the default type
(4) I get the size that I need (which is really all I care about)
(5) Resolved data type within the module if I make multiple-driver
assignments to the identifier
(6) Syntax error if I try to mix procedural and driver assignments to
the same variable
(7) Does not break any existing designs
If we implement this proposal, a user can select between:
(1) require all declarations
(2) declare the semi-universal "logic" type that prohibits multi-driver
resolution, or
(3) not require any of the common reg-wire declarations except for
internal sized identifiers, and they can all be called wire
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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