[sv-bc] parenthesis after an interface instantiation

Subject: [sv-bc] parenthesis after an interface instantiation
From: Jacobi, Dan (dan.jacobi@intel.com)
Date: Tue Feb 04 2003 - 01:08:29 PST

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It looks like there is one more place where the parenthesis
were forgotten after the interface instantiation .

under page 8 section 3.5 - I suggest to :

REPLACE:
        'interface' it ;
        'typedef' 'int' intP;
        'endinterface'
        it it1;
        'typedef' it1.intP intP;

WITH:
        'interface' it;
        'typedef' 'int' intP;
        'endinterface'
        it it1 ();
        'typedef' it1.intP intP;

We already accepted similar changes under section 13 of the System-Verilog
3.0 LRM.

Karen, Johny, I suggest we send this out for a quick E-mail vote.

Thanks Danny.

Dan Jacobi
Intel
Phone : (972)-4-8655855

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