Subject: [sv-bc] RE: [sv-ec] Agenda for Full SV meeting on February 28
From: David W. Smith (david.smith@synopsys.com)
Date: Mon Feb 10 2003 - 10:08:31 PST
I plan on being there (better since I have a presentation).
Regards
David
-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Vassilios.Gerousis@Infineon.Com
Sent: Monday, February 10, 2003 6:09 AM
To: sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
Subject: [sv-ec] Agenda for Full SV meeting on February 28
Importance: High
Hello SV Members,
The meeting for the SV committee (all four together) will mark the
third milestones that we set for ourselves. By this meeting, the contents of
SystemVerilog 3.1 has been defined. An assembly of the full LRM and review
can start taking into account the full 3.1.
The meeting will be hosted by Sun (to be confirmed soon). The host
agreed
to do this the week before, hopefully, they will extend the offer. I have
asked for 30 people max. If you need a conference call, please let me know.
We do plan to have one, but RSVP must apply to the call as well and if
specific time is required, it should be specified.
9:00 - 9:15 Introduction Vassilios Gerousis
9:15 - 10:15 SV committee status (all four committees). Each chair has 15
minutes.
SV Basic Johny Srouji / Karen Pieper
SV Assertion Faisal Haque.
SV C interface Swapnajit Mittra.
SV Enhancement David Smith.
10:15 - 10:30 Break
10:30 - 12:00 SV Chairs Synchronization
a- Scheduling semantics for SV 3.1 Discussions And
Decisions.
b- Task Force and Results on $root.
c- Static Decision.
d- Reference Implementation of SystemVerilog 3.1
12:00 - 12:30 Lunch
12:30 - 02:30 Review of the LRM 3.1 And Its Content
a- Assertion Final Contents And Compatibility with SystemVerilog
Syntax.
b- Testbench Final Contents.
c- Cross-Committees Topics and Resolution.
d- C interface.
e- SystemVerilog Basic Content
2:30 - 2:45 Break
2:45 - 3:00 Patent Discussions
Review Of Verisity Coverage Patent And Discussion.
3:00 - 4:00 3.1 LRM Process and Reviews.
4:00 - 4:30 Summary and Actions.
Best Regards
Vassilios
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Dr. Vassilios Gerousis
Chief Scientist
Infineon Technologies
DAT CS, MchB
D-81541 Munich
Germany
BalanSt. 73
Telephone: +49-89-234-21342
Fax: +49-89-234-23650
email: Vassilios.Gerousis@infineon.com
Site Map:
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