Subject: Re: [sv-bc] Proposal for extern modules
From: Dave Rich (David.Rich@synopsys.com)
Date: Fri Feb 14 2003 - 16:03:53 PST
I think there may be some confusion in the term "Separate Compilation"
for simulation vs.synthesis
Maybe "Independent Compilation" is a more accurate description of the
problem.
Synthesis tools would like to analyzes a module without seeing the
downmodule description. This can be done in verilog today because all
the tool needs to know is which signals are connected to ports. It
doesn't even need to know the type or direction of the port, just which
identifiers are going to cross a module boundary.
Yes, it is possible to restrict where .* can be used, but again, that
limits the usefulness of the feature
Dave
Steven Sharp wrote:
>I don't understand the need for this. I can see that it makes .* easier
>to implement, because the tool can expand the .* during parsing, and then
>doesn't have to worry about it any more. But the purpose of this is to
>be easier for the user, even if it requires extra effort from the tool.
>
>Separate compilation can just record that there was a .* on the port.
>Then during elaboration, when the instance is bound to a particular
>module definition, the ports will be known and the appropriate connections
>can be made. It isn't like you really know what is going on in a design
>until it is elaborated anyway. Are there tools that can do something
>useful with the partial information that is available before elaboration?
>
>Note that even if the modules are compiled together, you can't necessarily
>figure out the port connections for .* until elaboration. Verilog-2001
>configs allow an instance to be bound to different module declarations
>based on where the instance is in the hierarchy. I don't think there is
>any requirement that all the possible bindings for an instance have
>identical ports and port names.
>
>Different software architectures may give some tools a harder time in
>handling .* than others, and require a lot more work from the implementors.
>But I don't see anything inherently impossible about handling .* with
>separate compilation. It is just a matter of delaying yet another thing
>until elaboration.
>
>Steven Sharp
>sharp@cadence.com
>
>
>
>
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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