Subject: Re: [sv-bc] Proposal for extern modules
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Wed Feb 19 2003 - 17:52:22 PST
>
>If you have the real one, why would you need the dummy one? Why can't
>the tool do as Adam suggested and use the real port list? I can see
>that the proposal might allow the synthesis tool writer to avoid some
>work, but is there a benefit to the user?
The problem is that frequently in synthesis, formal verification, or even
static timing
analysis you don't have the real sub-design. A very common flow is for a
user to
synthesize and formally verify his "module" out of the context of the real
design.
Timing constraints are set at the ports to indicate the timing path
requirements
placed upon the module by the sub-design or super-design.
This flow frequently arises because there are a multitude of designers
working on
their own modules independent of the designers of other modules aside from a
description of ports, timing, area, and power budgets, etc.
It is important to allow users to tell tools the truth about the design,
and not lie to
them because of some insufficiency in the language.
Karen
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