Subject: [sv-bc] RE: [sv-ac] FW: [sv-ec] -- Location - Agenda for Full SV meeting on February 28
From: Vassilios.Gerousis@Infineon.Com
Date: Sun Feb 23 2003 - 10:22:46 PST
Hello Cindy,
There is no issue per se. The topic is synchronization.
The SV Chairs are making all efforts to synchronize all new
components that are being added to SystemVerilog 3.0. This include
SystemVerilog Design Core (SV-BC Committee), SystemVerilog TestBench (SV-EC
Committee), C/API interface (SV-CC committee) and of course SystemVerilog
Assertion (SV-AC Committee). When all those components are integrated, there
must be a formal way to schedule and define synchronization semantics among
these four major components. A proposal was provided in the last meeting of
the full committee (All information were sent on the email reflectors). You
can also find a large volume of information on the SV-EC reflector. This
assignment was given to SV-EC to finalize. You can also read about it in
SystemVerilog 3.1 Draft 3 LRM. After few months, we decided (SV Chairs) to
form a working group with top experts from each SV committee to resolve
issues with the proposal and enhance it to an acceptable level. After few
weeks, the working group has completed this with a unanimous vote to accept
and put this matter to the Full SV committee where it started in the first
place. My congratulation to this team, who worked through weekends and
nights to get this done, in this short period. This effort explifies the
teamwork and the original cooperation spirit that we have experienced with
SystemVerilog 3.0 standardization. My deep appreciation to the team members
and also to the leader David Smith.
By Monday, a voted document will be sent around to describe the final
proposal, and by Friday, the full committee will vote.
Cindy, as a representative of IBM, please join the meeting through a phone
or ask Yaron (attending DVCON) or other local IBM to attend in person. My
hope is that IBM will be supportive of SystemVerilog as a whole, and this
topic will be of great interest to IBM designers and verification engineers.
We have many different individuals that join each committee from a single
company. I know of few people, each is actively working in multiple SV
Committees at the same time. Examples are Bassam and Adam.
If this topic is of interest to you and IBM, please let me know be sending
me a direct email with the willingness to participate. I will discuss the
voting by email matter with both my chairs and also with Accellera Officers.
The current process is to allow voting by attendance in person or by phone.
This is why I have made it clear about voting in this committee and that is
why I do this full committee at certain milestones. However, this is not a
hard rule, and we would like to encourage IBM participation in other SV
committees.
Thanks for the interest and for your continued help in both FVTC and SV-AC.
Best Regards
Vassilios
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Dr. Vassilios Gerousis
Chief Scientist
Infineon Technologies
DAT CS, MchB
D-81541 Munich
Germany
BalanSt. 73
Telephone: +49-89-234-21342
Fax: +49-89-234-23650
email: Vassilios.Gerousis@infineon.com
Site Map:
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-----Original Message-----
From: Cindy Eisner [mailto:EISNER@il.ibm.com]
Sent: Sunday, February 23, 2003 8:10 AM
To: Gerousis Vassilios (CL DAT CS)
Cc: sv-ac@eda.org; sv-bc@eda.org; sv-ec@eda.org; sv-cc@eda.org
Subject: Re: [sv-ac] FW: [sv-ec] -- Location - Agenda for Full SV
meeting on February 28
vassilios,
>Please note, we will have our first vote in this committee.
what is the vote about? will the issue/s being voted on be presented
before the meeting by email? how is the vote conducted? i.e., do i have
to attend to vote in this meeting, or will it be possible to vote by email?
thanks,
cindy.
Cindy Eisner
Formal Methods Group Tel: +972-4-8296-266
IBM Haifa Research Laboratory Fax: +972-4-8296-114
Haifa 31905, Israel e-mail:
eisner@il.ibm.com
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