Subject: [sv-bc] Section 23 -- Compiler Directives (or Section 17 of 3.0LRM)
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Wed Feb 26 2003 - 08:35:00 PST
Section 23 (Compiler Directives) still needs some clarification --
1 ) In the introductory 23.1 --
SystemVerilog enhances the capabilities of the `define compiler
directive to support strings as macro arguments.
Is this trying to refer to the inclusion of macro arguments in strings?
Such a capability is mentioned in 23.2, but there is no example.
An example would be helpful.
2) According to 23.2, another way that SystemVerilog enhances the
capabilities
of the `define compiler directive is
to allow identifiers to be constructed from arguments.
Perhaps it, too, should be mentioned in the introduction.
3) In the first sentence of 23.2, 'SystemVerilog' should just be 'Verilog',
because using a backslash (\) to show continuation of a macro text on
the next line is already part of IEEE Std 1364-2001, Section 19.3.1.
4) According to 23.2 --
If the strings are to contain \", the macro text should be
written `\`". Otherwise, the backslash will be treated as
the start of an escaped identifier.
Is there something special about \", or would similar be true for the
other escape sequences, such as \n, \t, \\, \ddd?
5) In the example of 23.2, "foo(bar)" should be "`foo(bar)" with a tic.
6) What is meant by --
Note that there must be no space before the parenthesis.
? Which parenthesis? The one around formal arguments, the one around
actual arguments? Both? In any case, wouldn't the same be already
be true in Verilog?
-- Brad
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