[sv-bc] SV-BC 44

Subject: [sv-bc] SV-BC 44
From: Peter Flake (Peter.Flake@synopsys.com)
Date: Wed Feb 26 2003 - 16:21:20 PST


These are my proposals, which refer to SystemVerilog 3.1 Draft 2.

1.  Assignments as expressions should be left in the language, as no compelling argument has been given to remove them. The wording needs to be changed as follows in section 7.3:

REPLACE OLD
"Assignment operators may only be used with blocking assignments"
WITH NEW
"An assignment operator behaves like a blocking assignment with no timing control.  For example:
        a+=2;  // same as a=a+2;"
 
BEFORE "SystemVerilog also includes"
INSERT
The semantics of such an expression are those of a function which evaluates the right hand side, casts the right hand side to the left hand data type, stacks it, updates the left hand side and returns the stacked value.

2. In section 8.6 REMOVE
"A statement label does not create a hierarchy scope"

3.  It does not make sense to allow a continue or break in a dynamic process to affect its parent process.  For consistency, the same reasoning should apply to fork/join.  So a continue or break should be limited to a local loop in a single thread.

In Section 8.5 AFTER "jumps out of the loop"
INSERT
"The continue and break statements cannot be used inside a fork...join block to control a loop outside the fork...join block."


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