Subject: [sv-bc] Proposal for SV-BC42-23 .name ports
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Mar 03 2003 - 04:56:05 PST
Replace in section 12.7.2
"Implicit .name port connections do not have to be ordered the same as
the ports of the instantiated module.
The following rules apply to implicit .name port connections:
— For an implicit .name port connection to be legal, the connecting
variable name must match the port name
of the instantiated module.
— For an implicit .name port connection to be legal, the connecting
variable size must match the port size of
the instantiated module.
— For an implicit .name port connection to be legal, the connecting
variable data type must be compatible to
the port data type of the instantiated module. See section 12.7.5 for a
description of compatible data types
for implicit port connections.
— Implicit .name port connections cannot be used in the same
instantiation with positional port connections.
— Implicit .name port connections may be used in the same instantiation
with named port connections.
— Implicit .name port connections cannot be used in the same
instantiation with implicit .* port connections.
— The order of the implicit .name port connections does not have to
match the port-order of the instantiated
module.
— All connecting variables must be explicitly declared, either as a port
in the parent module (following the
rules of Verilog-2001) or as an explicit net or variable of one or more
bits."
with
A *.name* port connection is semantically equivalent to a *.name(name)*
port connection with the following exceptions:
— The identifier referenced by *.name* shall not create an implicit wire
declaration.
— It shall be an error if a *.name* port connection would create an
implicit cast. This includes truncation or padding.
"
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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