Subject: [sv-bc] %u and %z format specs (also $fread and $readmem{b,h})
From: Gordon Vreugdenhil (gvreugde@synopsys.com)
Date: Mon Mar 03 2003 - 14:21:49 PST
Here is my proposal for at least making some progress on the
file i/o extensions for SystemVerilog.
--------------
In Section 22.1:
CHANGE:
SystemVerilog adds several system tasks and system functions.
TO:
SystemVerilog adds system tasks and system functions as described
in the following sections. In addition, SystemVerilog extends the
behavior of the following:
o %u and %z format specifiers:
For packed data, %u and %z are defined to operate as though
the operation were applied to the equivalent vector.
For unpacked struct data, %u and %z are defined to apply as
though the operation were performed on each member in declaration
order.
For unpacked union data, %u and %z are defined to apply as
though the operation were performed on the first member in
declaration order.
%u and %z are not defined on unpacked arrays.
The "count" of data items read by a %u or %z for an aggregate
type is always either 1 or 0; the individual members are
not counted separately.
o $fread
$fread has two variants -- a "register" variant and a set
of three "memory" variants.
The "register" variant,
$fread(myreg, fd);
is defined to be the one applied for all packed data.
For unpacked struct data, $fread is defined to apply as
though the operation were performed on each member in
declaration order.
For unpacked union data, $fread is defined to apply as
though the operation were performed on the first member in
declaration order.
For unpacked arrays, the original definition applies except
that unpacked struct or union elements are read as described
above.
o $readmemb and $readmemh
$readmemb and $readmemh are extended to unpacked arrays
of packed data. In such cases, they treat each packed
element as the vector equivalent and perform the normal
operation. $readmemb and $readmemh are not defined for
packed arrays or unpacked arrays of unpacked data.
--------------------------
Note: It might be more clear to have section 22.2 describe extensions
to existing Verilog operations and have 22.3 and following describe the
new system functions and tasks.
Gord.
-- ---------------------------------------------------------------------- Gord Vreugdenhil gvreugde@synopsys.com Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054 Synopsys Inc., Beaverton OR
This archive was generated by hypermail 2b28 : Mon Mar 03 2003 - 14:22:49 PST