Subject: [sv-bc] Proposal for SV-BC42-11
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Mon Mar 03 2003 - 16:02:19 PST
Hi, all,
This proposal is to unify the operator priorities passed in the IEEE with
those in SystemVerilog.
In Table 7-2 from the 3.1 version 3 draft:
Replace the second row with:
+ - ! ~ & ~& | ~| ^ ~^ ^~ (unary)
Replace the fifth row with:
+ - (binary)
Replace the ninth row with:
& (binary)
Replace the tenth row with:
^ ~^ ^~ (binary)
Replace the 11th row with:
| (binary)
Replace the 14th row with:
?: (conditional operator)
Replace the 17th row with:
{} {{}}
The editors note for this table in the version 3 draft is correct that was
the right change.
K
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