Subject: Re: [sv-bc] Proposal for SV-BC75 declarations in unnamed blocks
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Mar 03 2003 - 17:07:05 PST
Steven,
You are correct in saying that the variables in the named block have the
same hierarchical name as if the unnamed block didn't have any variables
in it (no name component for the unnamed block).
The automatically generated block names are not visible to the
source.They are only used internal to the tools that need a placeholder
for the unnamed scope, creating a DAG in the hierarchy. Maybe this is
too much detail for the LRM and we should leave the auto generated names
out..
Dave
Steven Sharp wrote:
>
>Normally I would expect top.bar.r2 to be legal. It would be legal in
>Verilog now if the r1 declaration were removed. I don't see why adding
>the r1 declaration, which doesn't change the actual hierarchy, would
>make that illegal. But if the tool creates a generated name for the
>unnamed block scope, then it becomes impossible to use top.bar.r2. The
>name would have to be top.<generated_name>.bar.r2. This seems bad.
>Adding a new variable declaration into a block shouldn't make all the
>existing names in scopes inside that block change.
>
>But the solution to various issues that I raised with variables that
>don't have full path names was supposed to be the generation of these
>scope names. Eliminate the generated names, and those problems come
>back again.
>
>Steven Sharp
>sharp@cadence.com
>
>
>
>
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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