[sv-bc] Proposal for SV-BC-19-60

Subject: [sv-bc] Proposal for SV-BC-19-60
From: Jacobi, Dan (dan.jacobi@intel.com)
Date: Wed Mar 05 2003 - 07:51:08 PST

SV-BC listing
=============
This E-mail deals with the issue labeled as SV-BC-19-60

Motivation
==========
See my previous E-mail under
http://www.eda.org/vlog-pp/sv-bc/hm/0542.html

Proposal
=======

1. BNF changes
Using Brad's BNF proposal
 http://www.eda.org/vlog-pp/sv-bc/hm/0557.html

In A.1.4

ADD
   non_interface_port_declaration ::=
         { attribute_instance } inout_declaration
       | { attribute_instance } input_declaration
       | { attribute_instance } output_declaration
 
REPLACE
   port_declaration ::=
         { attribute_instance } inout_declaration
       | { attribute_instance } input_declaration
       | { attribute_instance } output_declaration
       | { attribute_instance } interface_port_declaration
WITH
   port_declaration ::=
         non_interface_port_declaration
       | { attribute_instance } interface_port_declaration 

---
In A.1.5

REPLACE
   module_item ::=
         port_declaration ';'
       | non_port_module_item
WITH
   module_item ::=
         non_interface_port_declaration ';'
       | non_port_module_item
---
In A.1.6 
REPLACE
   interface_item ::=
         port_declaration ';'
       | non_port_interface_item
WITH
   interface_item ::=
         non_interface_port_declaration ';'
       | non_port_interface_item

2. Language changes
Under 17.5 (referring to the System-Verilog 3.1 / Draft 3 ) 

Add the following paragraph to the end of the section:
"Generic interface ports cannot be declared using the Verilog 95 list of
ports style. Generic interface ports can only be declared by using a list of
port declaration style
	module cpuMod(interface d, interface j);
	...
	endmodule
"

Under 18.2.3
REPLACE
A module header can be created with an unspecified interface instantiation 
as a place-holder for an interface to be selected when the module itself 
is instantiated. The unspecified interface is referred to as a “generic”
interface port. 
The following interface example shows how to specify a generic interface
port in a 
module definition.
WITH
A module header can be created with an unspecified interface instantiation 
as a place-holder for an interface to be selected when the module itself 
is instantiated. The unspecified interface is referred to as a “generic”
interface port.
This generic interface port can only be declared by using the list of port
decleration style port declaration style. It will be illegal to declare such
a generic interface port
using the old Verilog 95 list of port style.
The following interface example shows how to specify a generic interface
port in a module definition.

Dan Jacobi
Phone : (972)-4-8655855

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