Subject: [sv-bc] proposal for conditional operator SV-BC62c
From: Dave Rich (David.Rich@synopsys.com)
Date: Wed Mar 05 2003 - 08:43:07 PST
Here is my proposal for SV-BC62c, to explain how the conditional operator works
on all the new systemverilog types. It turns out that SV-BC56 (allowed
operations on unpacked arrays) needs to be expanded to cover unpacked
structures. I include that as part of my proposal for SV-BC62c
Add at the end section 7 (Operators and Expressions)
7.12 Aggregate Expressions
Unpacked structure and array variables, literals, and expressions may all be
used as aggregate expressions. A multi-element slice of an unpacked array is may
also be used as an aggregate expression.
Aggregate expressions may be copied in an assignment, through a port, or as an
argument to a task or function. Aggregate expressions may also be compared with
equality or inequality operators. To be copied or compared, the type of an
aggregate expression must be equivalent.
Unpacked structures types are equivalent by the hierarchical name of its type
alone. This means in order to have two equivalent unpacked structures in two
different scopes, the type must be defined in one of the following ways:
- Defined in a higher-level scope common to both expressions.
- Passed through type parameter.
- Imported by hierarchical reference.
Unpacked arrays types are equivalent by having equivalent element types and
identical shape. Shape is defined as the number of dimensions and the number of
elements in each dimension, not the actual range of the dimension.
7.13 Conditional Operator
conditional_expression ::= (From Annex A - A.8.3)
expression1 ? { attribute_instance } expression2 : expression3
As defined in Verilog, if expression1 is true, the operator returns expression2,
if false, it returns expression3. If expression1 evaluates to ambiguous value (x
or z), then both expression2 and expression3 shall be evaluated and their
results shall be combined, bit by bit.
SystemVerilog extends the conditional operator to non bit-level types and
aggregate expressions using the following rules:
- If both expression2 and expression3 are bit-level types, or a packed aggregate
of bit type, the operation proceeds as defined.
- If expression2 or expression3 is a bit-level type and the opposing expression
can be implicitly cast to a bit-level type, the cast is made and proceeds as
defined.
- For all other cases, the type of expression2 and expression3 must be equivalent.
If expression1 evaluates to ambiguous value, then both expression2 and
expression3 shall be evaluated and their results shall be combined,
element-by-element. If the elements match, the element is returned. If they do
not match, then the default-uninitialized value for that element's type shall be
returned.
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