RE: [sv-bc] Updated Proposal for SV-BC-19-60 - take #3

Subject: RE: [sv-bc] Updated Proposal for SV-BC-19-60 - take #3
From: Jacobi, Dan (dan.jacobi@intel.com)
Date: Thu Mar 06 2003 - 10:13:21 PST

I fixed the original proposal - I hope that it is O.K. now

>-----Original Message-----
>From: Brad Pierce [mailto:Brad.Pierce@synopsys.com]
>Sent: Thursday, March 06, 2003 9:20 AM
>To: sv-bc@eda.org
>Subject: Re: [sv-bc] Updated Proposal for SV-BC-19-60
>
>
>Dan asked me to double-check for typos before he sent his updated proposal
>to the reflector.
>It looked good to me. So, of course, as soon as he sends it to the
>reflector, THEN I see a typo!
>
>The "non_interface_port_declaration" in A.1.6 should be
>."non_generic_port_declaration"..
>
>Sorry, Dan!
>
>-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Jacobi,
Dan
Sent: Wednesday, March 05, 2003 11:13 PM
To: sv-bc@eda.org
Subject: [sv-bc] Updated Proposal for SV-BC-19-60

I hope I got it right this time ...

SV-BC listing
=============
This E-mail deals with the issue labeled as SV-BC-19-60

Motivation
==========
See my previous E-mail under
http://www.eda.org/vlog-pp/sv-bc/hm/0542.html

In General
==========
We want to enable the use of such kinds of RTL:
        module m1(interface p1,interface p2);
        ...
        endmodule

        interface i1(interface p1,interface p2);
        ...
        endinterface

        ...
        module m1(p1,p2);
        simple_bus p1;
        simple_bus p2;
        ...
        endmodule

However the following RTL should NOT be supported
        module m1(p1,p2);
        interface p1;
        interface p2;
        ...
        endmodule

        interface i1(p1,p2);
        interface p1;
        interface p2;
        ...
        endinterface

Proposal
========

1. BNF changes

In A.1.4

ADD
   non_generic_port_declaration ::=
         { attribute_instance } inout_declaration
       | { attribute_instance } input_declaration
       | { attribute_instance } output_declaration
         | interface_port_declaration

REPLACE
   port_declaration ::=
         { attribute_instance } inout_declaration
       | { attribute_instance } input_declaration
       | { attribute_instance } output_declaration
       | { attribute_instance } interface_port_declaration
WITH
   port_declaration ::=
         non_generic_port_declaration
       | { attribute_instance } generic_interface_port_declaration 

---
In A.1.5

REPLACE
   module_item ::=
         port_declaration ';'
       | non_port_module_item
WITH
   module_item ::=
         non_generic_port_declaration ';'
       | non_port_module_item

---
In A.1.6
REPLACE
   interface_item ::=
         port_declaration ';'
       | non_port_interface_item
WITH
   interface_item ::=
         non_generic_port_declaration ';'
       | non_port_interface_item

Under A.2.1.2
ADD
	generic_interface_port_declaration ::=
		'interface' list_of_interface_identifiers
		| 'interface' '.' modport_identifier
list_of_interface_identifiers

REPLACE
	interface_port_declaration ::=
		'interface' list_of_interface_identifiers
		| 'interface' '.' modport_identifier
list_of_interface_identifiers
		| interface_identifier list_of_interface_identifiers
		| interface_identifier . modport_identifier
list_of_interface_identifiers
WITH
	interface_port_declaration ::=
		 interface_identifier list_of_interface_identifiers
		| interface_identifier . modport_identifier
list_of_interface_identifiers

2. Language changes
Under 17.5 (referring to the System-Verilog 3.1 / Draft 3 )

Add the following paragraph to the end of the section:
"Generic interface ports cannot be declared using the Verilog 95 list of
ports style. Generic interface ports can only be declared by using a list of
port declaration style
	module cpuMod(interface d, interface j);
	...
	endmodule
"

Under 18.2.3
REPLACE
A module header can be created with an unspecified interface instantiation
as a place-holder for an interface to be selected when the module itself
is instantiated. The unspecified interface is referred to as a “generic”
interface port.
The following interface example shows how to specify a generic interface
port in a
module definition.
WITH
A module header can be created with an unspecified interface instantiation
as a place-holder for an interface to be selected when the module itself
is instantiated. The unspecified interface is referred to as a “generic”
interface port.
This generic interface port can only be declared by using the list of port
decleration style port declaration style. It will be illegal to declare such
a generic interface port
using the old Verilog 95 list of port style.
The following interface example shows how to specify a generic interface
port in a module definition.

Dan Jacobi
Phone : (972)-4-8655855

This archive was generated by hypermail 2b28 : Thu Mar 06 2003 - 10:17:44 PST