Subject: [sv-bc] SV-BC75: variables in unnamed blocks
From: Francoise Martinolle (fm@cadence.com)
Date: Thu Mar 06 2003 - 14:30:47 PST
Dave,
given the email feedback on this, I think this has to be reworded.
In particular the sentence about hierarchical references is too vague.
and we want to suppress the auto-generated scope name
Disagree with the wording
:
WITH
"Note that in SystemVerilog, data can be declared in unnamed blocks as
well as in named blocks. This data is visible to the unnamed block and
any nested blocks below it. Hierarchical references cannot be used to
access this data by name. Some tools may automatically generate scope
names for data in these unnamed blocks, however, these generated scope
names shall not be visible to the scopes below it."
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