Subject: Re: [sv-bc] SV-BC75: variables in unnamed blocks
From: Francoise Martinolle (fm@cadence.com)
Date: Fri Mar 07 2003 - 07:49:45 PST
I don't know exactly how to say it but we need to mention that unnamed
blocks are scopes which do not create a hierarchical instance. I mean that
if you had to create a hierarchical name which would pass through an
unnamed block, the unnamed block would be skipped since it has no name.
May be something like, "an unnamed block is a scope with no name and so a
hierarchical name through that block would be equivalent to the
hierarchical produced as if the unnamed
block did not exist."
Francoise
'
At 11:59 PM 3/6/2003 -0800, Dave Rich wrote:
>OK, I'll remove the last sentence.
>
>Would this wording be clearer:
>
>"Note that in SystemVerilog, data can be declared in unnamed blocks as
>well as in named blocks. This data is visible to the unnamed block and any
>nested blocks below it. References via hierarchical identifiers to this
>data are not available."
>
>
>Francoise Martinolle wrote:
>
>>Dave,
>>
>>given the email feedback on this, I think this has to be reworded.
>>In particular the sentence about hierarchical references is too vague.
>>and we want to suppress the auto-generated scope name
>>
>>Disagree with the wording
>>:
>>WITH
>>"Note that in SystemVerilog, data can be declared in unnamed blocks as
>>well as in named blocks. This data is visible to the unnamed block and
>>any nested blocks below it. Hierarchical references cannot be used to
>>access this data by name. Some tools may automatically generate scope
>>names for data in these unnamed blocks, however, these generated scope
>>names shall not be visible to the scopes below it."
>
>--
>--
>Dave Rich
>Principal Engineer, CAE, VTG
>Tel: 650-584-4026
>Cell: 510-589-2625
>DaveR@Synopsys.com
>
>
This archive was generated by hypermail 2b28 : Fri Mar 07 2003 - 07:50:16 PST