[sv-bc] External data proposal
Subject: [sv-bc] External data proposal
From: Peter Flake (Peter.Flake@synopsys.com)
Date: Fri Mar 14 2003 - 07:04:55 PST
ADD to draft 3 a new section 5.8
5.8 External data
Some tools require each module to be analyzed separately. If the
module uses variables declared in $root, the names and types need to
be visible to the analysis to allow checking. However it is
important that each analysis does not create its own copy of the
variable.
SystemVerilog allows the existence elsewhere of a variable name and type
to be declared using the extern keyword. For example
extern
int mymod_i;
This external data declaration can only be used in $root. The same
name can be declared with the same data type more than once.
External data declarations of a name require a matching data declaration
(with the same data type) somewhere else in the $root scope, otherwise
there is an elaboration error. For example:
int
mymod_i;
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: Fri Mar 14 2003 - 07:38:49 PST