Subject: Re: [sv-bc] External Functions and Tasks proposal
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Fri Mar 14 2003 - 10:13:16 PST
I requested that the extern module syntax be extended to be terminated
with "endmodule" (there wasn't
a response), that would allow external declaration of tasks/functions in
modules e.g.:
extern module foo;
function int func1(int I); // no body allowed
endmodule
If folks don't particularly want to do that now but might later, the
"endmodule" needs to be in the syntax
for the extern module declaration.
Kev.
Peter Flake wrote:
> ADD to draft 3 new section 10.6
>
> 5.8 External tasks and functions
>
> Some tools require each module to be analyzed separately. If the
> module uses tasks or functions declared in $root, the names and
> argument types need to be visible to the analysis to allow checking.
> However it is important that each analysis does not create its own
> copy of the task or function.
>
> SystemVerilog allows the existence elsewhere of a task or function
> name and prototype to be declared using the extern keyword. For example
> extern function int func1(int I);
>
> If this external declaration is in $root, the same name can be
> declared with the same prototype more than once.
>
> A declarations of a task or function prototype requires a matching
> declaration (with the same arguments) somewhere else , otherwise there
> is an elaboration error. For example:
> function int func1(int I);
> return I;
> endfunction
>
> If the prototype is in the $root scope, the task or function must be
> declared in the $root scope.
>
> If the prototype is in an interface, the task or function must be
> declared in one of the modules connected to an instance of that interface.
>
> If the prototype is a class, the task or function must be declared as
> an out-of-body method (see section 11.20).
>
>
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