Subject: [sv-bc] SystemVerilog 3.1 LRM, draft 4
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Fri Apr 04 2003 - 03:42:07 PST
All,
Draft 4 of the SystemVerilog 3.1 LRM is now available for download and
review. This draft includes an up-to-date BNF (Annex A) as well as a
massive number of changes from the BC and EC committees. It also includes
an updated section on assertions from the AC committee, and several new
sections from the CC committee.
You can download the draft from the following link:
http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft4.pdf
Colors and underlining have been used to make it obvious what text is new,
or to be deleted. A legend right at the beginning explains how changes are
marked. Old changes from drafts 1 to 3 are in blue text. The changes from
the EC, CC and AC are in blue underlined text, and changes from the BC are
in red underlined text. Boxes in the margin provide cross references to
the change order numbers from the EC and BC committees. Change order
numbers for draft 4 are in red.
I will prepare a "clean" version of draft 4 in a few days, with all
to-be-deleted text removed, and all color coding and note boxes removed.
Enjoy the leisure reading this weekend!
Stu
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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